ADC (M8, R8h)
Summary:
"Add with Carry"
Reference:
https://www.felixcloutier.com/x86/ADC.html
Extension:
BASE
Category:
BINARY
ISA-Set:
I86
CPL:
3
iform:
ADC_MEMb_GPR8
iclass:
ADC
ASM:
ADC
Operands
Operand 1 (r/w): Memory
Operand 2 (r): Register (AH, CH, DH, BH)
Operand 3 (r/w, suppressed): Flags (AF: w, CF: r/w, OF: w, PF: w, SF: w, ZF: w)
Available performance data
Alder Lake-P
Alder Lake-E
Rocket Lake
Tiger Lake
Ice Lake
Cascade Lake
Cannon Lake
Skylake-X
Coffee Lake
Kaby Lake
Skylake
Broadwell
Haswell
Ivy Bridge
Sandy Bridge
Westmere
Nehalem
Wolfdale
Conroe
Tremont
Goldmont Plus
Goldmont
Airmont
Bonnell
AMD Zen 4
AMD Zen 3
AMD Zen 2
AMD Zen+
Alder Lake-P
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤13
Latency operand 1 → 1 (address, index register):
≤13
Latency operand 1 → 1 (memory):
7
Latency operand 1 → 3 (address, base register):
7
Latency operand 1 → 3 (address, index register):
7
Latency operand 1 → 3 (memory):
≤7
Latency operand 2 → 1:
≤12
Latency operand 2 → 3:
≤7
Latency operand 3 → 1:
≤6
Latency operand 3 → 3:
2
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.25
Measured (unrolled):
1.40
Number of μops
Executed: 6
Retire slots: 5
Decoded (MITE): 5
Microcode Sequencer (MS): 0
Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p0156B+1*p06+1*p1+1*p23A+1*p49+1*p78
Alder Lake-E
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤7
Latency operand 1 → 1 (address, index register):
≤7
Latency operand 1 → 1 (memory):
2
Latency operand 1 → 3 (address, base register):
0
Latency operand 1 → 3 (address, index register):
0
Latency operand 1 → 3 (memory):
≤2
Latency operand 2 → 1:
≤2
Latency operand 2 → 3:
1
Latency operand 3 → 1:
≤2
Latency operand 3 → 3:
2
Throughput
Measured (loop):
0.75
Measured (unrolled):
0.75
Number of μops
Executed: 1
Microcode Sequencer (MS): 0
Rocket Lake
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤18
Latency operand 1 → 1 (address, index register):
≤18
Latency operand 1 → 1 (memory):
9
Latency operand 1 → 3 (address, base register):
9
Latency operand 1 → 3 (address, index register):
9
Latency operand 1 → 3 (memory):
≤9
Latency operand 2 → 1:
≤12
Latency operand 2 → 3:
≤5
Latency operand 3 → 1:
≤6
Latency operand 3 → 3:
1
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.52 (if an indexed addressing mode is used: 1.20)
Measured (unrolled):
1.54 (if an indexed addressing mode is used: 1.10)
Number of μops
Executed: 6
Retire slots: 4 (if an indexed addressing mode is used: 5)
Decoded (MITE): 4
Microcode Sequencer (MS): 0
Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p0156+2*p06+1*p23+1*p49+1*p78
Tiger Lake
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤18
Latency operand 1 → 1 (address, index register):
≤18
Latency operand 1 → 1 (memory):
9
Latency operand 1 → 3 (address, base register):
9
Latency operand 1 → 3 (address, index register):
9
Latency operand 1 → 3 (memory):
≤9
Latency operand 2 → 1:
≤12
Latency operand 2 → 3:
≤5
Latency operand 3 → 1:
≤6
Latency operand 3 → 3:
1
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.50 (if an indexed addressing mode is used: 1.25)
Measured (unrolled):
1.56 (if an indexed addressing mode is used: 1.20)
Number of μops
Executed: 6
Retire slots: 4 (if an indexed addressing mode is used: 5)
Decoded (MITE): 4
Microcode Sequencer (MS): 0
Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p0156+2*p06+1*p23+1*p49+1*p78
Ice Lake
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤18
Latency operand 1 → 1 (address, index register):
≤18
Latency operand 1 → 1 (memory):
9
Latency operand 1 → 3 (address, base register):
9
Latency operand 1 → 3 (address, index register):
9
Latency operand 1 → 3 (memory):
≤9
Latency operand 2 → 1:
≤12
Latency operand 2 → 3:
≤5
Latency operand 3 → 1:
≤6
Latency operand 3 → 3:
1
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.50 (if an indexed addressing mode is used: 1.25)
Measured (unrolled):
1.58 (if an indexed addressing mode is used: 1.20)
Number of μops
Executed: 6
Retire slots: 4 (if an indexed addressing mode is used: 5)
Decoded (MITE): 4
Microcode Sequencer (MS): 0
Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p0156+2*p06+1*p23+1*p49+1*p78
Cascade Lake
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤12
Latency operand 1 → 1 (address, index register):
≤12
Latency operand 1 → 1 (memory):
5
Latency operand 1 → 3 (address, base register):
7
Latency operand 1 → 3 (address, index register):
7
Latency operand 1 → 3 (memory):
≤4
Latency operand 2 → 1:
≤4
Latency operand 2 → 3:
2
Latency operand 3 → 1:
≤5
Latency operand 3 → 3:
1
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.47 (if an indexed addressing mode is used: 1.58)
Measured (unrolled):
1.67
Number of μops
Executed: 6
Retire slots: 4 (if an indexed addressing mode is used: 5)
Decoded (MITE): 4
Microcode Sequencer (MS): 0
Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0156+2*p06+2*p23+1*p4)
Cannon Lake
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤12
Latency operand 1 → 1 (address, index register):
≤12
Latency operand 1 → 1 (memory):
5
Latency operand 1 → 3 (address, base register):
7
Latency operand 1 → 3 (address, index register):
7
Latency operand 1 → 3 (memory):
≤4
Latency operand 2 → 1:
≤4
Latency operand 2 → 3:
2
Latency operand 3 → 1:
≤5
Latency operand 3 → 3:
1
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.47 (if an indexed addressing mode is used: 1.50)
Measured (unrolled):
1.75 (if an indexed addressing mode is used: 1.50)
Number of μops
Executed: 6
Retire slots: 4 (if an indexed addressing mode is used: 5)
Decoded (MITE): 4
Microcode Sequencer (MS): 0
Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0156+2*p06+2*p23+1*p4)
Skylake-X
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤11
Latency operand 1 → 1 (address, index register):
≤13
Latency operand 1 → 1 (memory):
5
Latency operand 1 → 3 (address, base register):
7
Latency operand 1 → 3 (address, index register):
7
Latency operand 1 → 3 (memory):
≤4
Latency operand 2 → 1:
≤4
Latency operand 2 → 3:
2
Latency operand 3 → 1:
≤5
Latency operand 3 → 3:
1
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.47 (if an indexed addressing mode is used: 1.60)
Measured (unrolled):
1.25 (if an indexed addressing mode is used: 1.55)
Number of μops
Executed: 6
Retire slots: 4 (if an indexed addressing mode is used: 5)
Decoded (MITE): 4
Microcode Sequencer (MS): 0
Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0156+2*p06+2*p23+1*p4)
IACA 2.3
Throughput
Computed from the port usage: 1.00
IACA:
1.24
Number of μops:
6
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4
IACA 3.0
Throughput
Computed from the port usage: 1.00
IACA:
1.00
Number of μops:
6
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4
Coffee Lake
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤12
Latency operand 1 → 1 (address, index register):
≤12
Latency operand 1 → 1 (memory):
5
Latency operand 1 → 3 (address, base register):
7
Latency operand 1 → 3 (address, index register):
7
Latency operand 1 → 3 (memory):
≤4
Latency operand 2 → 1:
≤4
Latency operand 2 → 3:
2
Latency operand 3 → 1:
≤5
Latency operand 3 → 3:
1
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.45 (if an indexed addressing mode is used: 1.55)
Measured (unrolled):
1.16 (if an indexed addressing mode is used: 1.58)
Number of μops
Executed: 6
Retire slots: 4 (if an indexed addressing mode is used: 5)
Decoded (MITE): 4
Microcode Sequencer (MS): 0
Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0156+2*p06+2*p23+1*p4)
Kaby Lake
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤12
Latency operand 1 → 1 (address, index register):
≤13
Latency operand 1 → 1 (memory):
5
Latency operand 1 → 3 (address, base register):
7
Latency operand 1 → 3 (address, index register):
7
Latency operand 1 → 3 (memory):
≤4
Latency operand 2 → 1:
≤4
Latency operand 2 → 3:
2
Latency operand 3 → 1:
≤5
Latency operand 3 → 3:
1
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.47 (if an indexed addressing mode is used: 1.54)
Measured (unrolled):
1.22 (if an indexed addressing mode is used: 1.53)
Number of μops
Executed: 6
Retire slots: 4 (if an indexed addressing mode is used: 5)
Decoded (MITE): 4
Microcode Sequencer (MS): 0
Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0156+2*p06+2*p23+1*p4)
Skylake
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤12
Latency operand 1 → 1 (address, index register):
≤12
Latency operand 1 → 1 (memory):
5
Latency operand 1 → 3 (address, base register):
7
Latency operand 1 → 3 (address, index register):
7
Latency operand 1 → 3 (memory):
≤4
Latency operand 2 → 1:
≤4
Latency operand 2 → 3:
2
Latency operand 3 → 1:
≤5
Latency operand 3 → 3:
1
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.45 (if an indexed addressing mode is used: 1.58)
Measured (unrolled):
1.17 (if an indexed addressing mode is used: 1.63)
Number of μops
Executed: 6
Retire slots: 4 (if an indexed addressing mode is used: 5)
Decoded (MITE): 4
Microcode Sequencer (MS): 0
Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0156+2*p06+2*p23+1*p4)
IACA 2.3
Throughput
Computed from the port usage: 1.00
IACA:
1.24
Number of μops:
6
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4
IACA 3.0
Throughput
Computed from the port usage: 1.00
IACA:
1.00
Number of μops:
6
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4
Broadwell
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤14
Latency operand 1 → 1 (address, index register):
≤13
Latency operand 1 → 1 (memory):
7
Latency operand 1 → 3 (address, base register):
7
Latency operand 1 → 3 (address, index register):
7
Latency operand 1 → 3 (memory):
≤7
Latency operand 2 → 1:
≤6
Latency operand 2 → 3:
2
Latency operand 3 → 1:
≤6
Latency operand 3 → 3:
2
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.60 (if an indexed addressing mode is used: 1.62)
Measured (unrolled):
2.00 (if an indexed addressing mode is used: 1.60)
Number of μops
Executed: 6
Retire slots: 4 (if an indexed addressing mode is used: 5)
Decoded (MITE): 4
Microcode Sequencer (MS): 0
Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0156+2*p06+2*p23+1*p4)
IACA 2.2
Throughput
Computed from the port usage: 1.00
IACA:
1.25 (with the -no_interiteration flag: 1.67)
Number of μops:
6
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4
IACA 2.3
Throughput
Computed from the port usage: 1.00
IACA:
1.24
Number of μops:
6
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4
IACA 3.0
Throughput
Computed from the port usage: 1.00
IACA:
1.10
Number of μops:
6
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4
Haswell
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤14
Latency operand 1 → 1 (address, index register):
≤11
Latency operand 1 → 1 (memory):
7
Latency operand 1 → 3 (address, base register):
7
Latency operand 1 → 3 (address, index register):
7
Latency operand 1 → 3 (memory):
≤6
Latency operand 2 → 1:
≤6
Latency operand 2 → 3:
2
Latency operand 3 → 1:
≤6
Latency operand 3 → 3:
1
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.69
Measured (unrolled):
1.87 (if an indexed addressing mode is used: 1.71)
Number of μops
Executed: 6
Retire slots: 4 (if an indexed addressing mode is used: 5)
Decoded (MITE): 4
Microcode Sequencer (MS): 0
Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0156+2*p06+2*p23+1*p4)
IACA 2.1
Latency:
9
Throughput
Computed from the port usage: 1.00
IACA:
1.25 (with the -no_interiteration flag: 1.00)
Number of μops:
6
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4
IACA 2.2
Throughput
Computed from the port usage: 1.00
IACA:
1.25 (with the -no_interiteration flag: 1.43)
Number of μops:
6
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4
IACA 2.3
Throughput
Computed from the port usage: 1.00
IACA:
1.24
Number of μops:
6
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4
IACA 3.0
Throughput
Computed from the port usage: 1.00
IACA:
1.00
Number of μops:
6
Port usage:
1*p0156+2*p06+1*p23+1*p237+1*p4
Ivy Bridge
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤11
Latency operand 1 → 1 (address, index register):
≤10
Latency operand 1 → 1 (memory):
7
Latency operand 1 → 3 (address, base register):
7
Latency operand 1 → 3 (address, index register):
7
Latency operand 1 → 3 (memory):
≤6
Latency operand 2 → 1:
≤6
Latency operand 2 → 3:
2
Latency operand 3 → 1:
≤6
Latency operand 3 → 3:
1
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.60 (if an indexed addressing mode is used: 2.00)
Measured (unrolled):
1.63 (if an indexed addressing mode is used: 2.00)
Number of μops
Executed: 6
Retire slots: 4 (if an indexed addressing mode is used: 6)
Decoded (MITE): 4
Microcode Sequencer (MS): 0
Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p015+2*p05+2*p23+1*p4
IACA 2.1
Latency:
9
Throughput
Computed from the port usage: 1.00
IACA:
1.33 (with the -no_interiteration flag: 1.00)
Number of μops:
6
Port usage:
1*p015+2*p05+2*p23+1*p4
IACA 2.2
Throughput
Computed from the port usage: 1.00
IACA:
1.33 (with the -no_interiteration flag: 1.67)
Number of μops:
6
Port usage:
1*p015+2*p05+2*p23+1*p4
IACA 2.3
Throughput
Computed from the port usage: 1.00
IACA:
1.33
Number of μops:
6
Port usage:
1*p015+2*p05+2*p23+1*p4
Sandy Bridge
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤11
Latency operand 1 → 1 (address, index register):
≤10
Latency operand 1 → 1 (memory):
7
Latency operand 1 → 3 (address, base register):
7
Latency operand 1 → 3 (address, index register):
7
Latency operand 1 → 3 (memory):
≤6
Latency operand 2 → 1:
≤6
Latency operand 2 → 3:
2
Latency operand 3 → 1:
≤6
Latency operand 3 → 3:
1
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.65 (if an indexed addressing mode is used: 2.00)
Measured (unrolled):
1.65 (if an indexed addressing mode is used: 2.00)
Number of μops
Executed: 6
Retire slots: 4 (if an indexed addressing mode is used: 6)
Decoded (MITE): 4
Microcode Sequencer (MS): 0
Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p015+2*p05+2*p23+1*p4
IACA 2.1
Latency:
9
Throughput
Computed from the port usage: 1.00
IACA:
1.33 (with the -no_interiteration flag: 1.00)
Number of μops:
6
Port usage:
1*p015+2*p05+2*p23+1*p4
IACA 2.2
Throughput
Computed from the port usage: 1.00
IACA:
1.33 (with the -no_interiteration flag: 1.67)
Number of μops:
6
Port usage:
1*p015+2*p05+2*p23+1*p4
IACA 2.3
Throughput
Computed from the port usage: 1.00
IACA:
1.33
Number of μops:
6
Port usage:
1*p015+2*p05+2*p23+1*p4
Westmere
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤8
Latency operand 1 → 1 (address, index register):
≤8
Latency operand 1 → 1 (memory):
6
Latency operand 1 → 3 (address, base register):
6
Latency operand 1 → 3 (address, index register):
6
Latency operand 1 → 3 (memory):
≤6
Latency operand 2 → 1:
≤5
Latency operand 2 → 3:
1
Latency operand 3 → 1:
≤8
Latency operand 3 → 3:
3
Throughput
Computed from the port usage: 1.00
Measured (loop):
2.00 (if an indexed addressing mode is used: 2.08)
Measured (unrolled):
2.00
Number of μops
Executed: 6
Retire slots: 4 (if an indexed addressing mode is used: 6)
Microcode Sequencer (MS): 0
Requires the complex decoder
Port usage:
3*p015+1*p2+1*p3+1*p4
IACA 2.1
Latency:
8
Throughput
Computed from the port usage: 1.00
IACA:
1.33 (with the -no_interiteration flag: 1.00)
Number of μops:
6
Port usage:
3*p015+1*p2+1*p3+1*p4
IACA 2.2
Throughput
Computed from the port usage: 1.00
IACA:
1.33 (with the -no_interiteration flag: 1.62)
Number of μops:
6
Port usage:
3*p015+1*p2+1*p3+1*p4
Nehalem
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤8
Latency operand 1 → 1 (address, index register):
≤8
Latency operand 1 → 1 (memory):
6
Latency operand 1 → 3 (address, base register):
6
Latency operand 1 → 3 (address, index register):
6
Latency operand 1 → 3 (memory):
≤6
Latency operand 2 → 1:
≤5
Latency operand 2 → 3:
1
Latency operand 3 → 1:
≤8
Latency operand 3 → 3:
3
Throughput
Computed from the port usage: 1.00
Measured (loop):
2.00 (if an indexed addressing mode is used: 2.08)
Measured (unrolled):
2.00
Number of μops
Executed: 6
Retire slots: 4 (if an indexed addressing mode is used: 6)
Microcode Sequencer (MS): 0
Requires the complex decoder
Port usage:
3*p015+1*p2+1*p3+1*p4
IACA 2.1
Latency:
8
Throughput
Computed from the port usage: 1.00
IACA:
1.33 (with the -no_interiteration flag: 1.00)
Number of μops:
6
Port usage:
3*p015+1*p2+1*p3+1*p4
IACA 2.2
Throughput
Computed from the port usage: 1.00
IACA:
1.33 (with the -no_interiteration flag: 1.62)
Number of μops:
6
Port usage:
3*p015+1*p2+1*p3+1*p4
Wolfdale
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤10
Latency operand 1 → 1 (address, index register):
≤10
Latency operand 1 → 1 (memory):
6
Latency operand 1 → 3 (address, base register):
7
Latency operand 1 → 3 (address, index register):
6
Latency operand 1 → 3 (memory):
≤7
Latency operand 2 → 1:
≤5
Latency operand 2 → 3:
2
Latency operand 3 → 1:
≤7
Latency operand 3 → 3:
2
Throughput
Computed from the port usage: 1.00
Measured (loop):
2.09
Measured (unrolled):
2.25
Number of μops
Executed: 6
Port usage:
3*p015+1*p2+1*p3+1*p4
Conroe
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤10
Latency operand 1 → 1 (address, index register):
≤10
Latency operand 1 → 1 (memory):
6
Latency operand 1 → 3 (address, base register):
7
Latency operand 1 → 3 (address, index register):
6
Latency operand 1 → 3 (memory):
≤7
Latency operand 2 → 1:
≤5
Latency operand 2 → 3:
2
Latency operand 3 → 1:
≤7
Latency operand 3 → 3:
2
Throughput
Computed from the port usage: 1.00
Measured (loop):
2.50
Measured (unrolled):
2.43
Number of μops
Executed: 6
Port usage:
3*p015+1*p2+1*p3+1*p4
Tremont
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤10
Latency operand 1 → 1 (address, index register):
≤10
Latency operand 1 → 1 (memory):
7
Latency operand 1 → 3 (address, base register):
5
Latency operand 1 → 3 (address, index register):
5
Latency operand 1 → 3 (memory):
≤6
Latency operand 2 → 1:
≤7
Latency operand 2 → 3:
≤3
Latency operand 3 → 1:
≤7
Latency operand 3 → 3:
2
Throughput
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 1
Microcode Sequencer (MS): 0
Goldmont Plus
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤10
Latency operand 1 → 1 (address, index register):
≤10
Latency operand 1 → 1 (memory):
6
Latency operand 1 → 3 (address, base register):
5
Latency operand 1 → 3 (address, index register):
5
Latency operand 1 → 3 (memory):
≤6
Latency operand 2 → 1:
≤6
Latency operand 2 → 3:
≤3
Latency operand 3 → 1:
≤6
Latency operand 3 → 3:
2
Throughput
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 1
Microcode Sequencer (MS): 0
Goldmont
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤10
Latency operand 1 → 1 (address, index register):
≤10
Latency operand 1 → 1 (memory):
4
Latency operand 1 → 3 (address, base register):
5
Latency operand 1 → 3 (address, index register):
5
Latency operand 1 → 3 (memory):
≤6
Latency operand 2 → 1:
≤6
Latency operand 2 → 3:
≤3
Latency operand 3 → 1:
≤6
Latency operand 3 → 3:
2
Throughput
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 1
Microcode Sequencer (MS): 0
Airmont
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤9
Latency operand 1 → 1 (address, index register):
≤9
Latency operand 1 → 1 (memory):
6
Latency operand 1 → 3 (address, base register):
5
Latency operand 1 → 3 (address, index register):
5
Latency operand 1 → 3 (memory):
≤5
Latency operand 2 → 1:
≤5
Latency operand 2 → 3:
≤2
Latency operand 3 → 1:
≤6
Latency operand 3 → 3:
2
Throughput
Measured (loop):
2.00
Measured (unrolled):
2.00
Number of μops
Executed: 1
Microcode Sequencer (MS): 0
Bonnell
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤4
Latency operand 1 → 1 (address, index register):
≤4
Latency operand 1 → 1 (memory):
1
Latency operand 1 → 3 (address, base register):
4
Latency operand 1 → 3 (address, index register):
4
Latency operand 1 → 3 (memory):
≤1
Latency operand 2 → 1:
≤2
Latency operand 2 → 3:
≤3
Latency operand 3 → 1:
≤2
Latency operand 3 → 3:
2
Throughput
Measured (loop):
2.00
Measured (unrolled):
2.00
Number of μops
Executed: 1
Microcode Sequencer (MS): 0
AMD Zen 4
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤11
Latency operand 1 → 1 (address, index register):
≤11
Latency operand 1 → 1 (memory):
5
Latency operand 1 → 3 (address, base register):
5
Latency operand 1 → 3 (address, index register):
5
Latency operand 1 → 3 (memory):
≤7
Latency operand 2 → 1:
≤6
Latency operand 2 → 3:
1
Latency operand 3 → 1:
≤7
Latency operand 3 → 3:
1
Throughput
Measured (loop):
0.60
Measured (unrolled):
0.83
Number of μops
Executed: 2
AMD Zen 3
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤11
Latency operand 1 → 1 (address, index register):
≤11
Latency operand 1 → 1 (memory):
5
Latency operand 1 → 3 (address, base register):
5
Latency operand 1 → 3 (address, index register):
5
Latency operand 1 → 3 (memory):
≤7
Latency operand 2 → 1:
≤6
Latency operand 2 → 3:
1
Latency operand 3 → 1:
≤7
Latency operand 3 → 3:
1
Throughput
Measured (loop):
0.60
Measured (unrolled):
0.60
Number of μops
Executed: 1
AMD Zen 2
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤9
Latency operand 1 → 1 (address, index register):
≤9
Latency operand 1 → 1 (memory):
7
Latency operand 1 → 3 (address, base register):
5
Latency operand 1 → 3 (address, index register):
5
Latency operand 1 → 3 (memory):
≤7
Latency operand 2 → 1:
≤7
Latency operand 2 → 3:
1
Latency operand 3 → 1:
≤7
Latency operand 3 → 3:
1
Throughput
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 1
AMD Zen+
Measurements
Latencies
Latency operand 1 → 1 (address, base register):
≤9
Latency operand 1 → 1 (address, index register):
≤9
Latency operand 1 → 1 (memory):
7
Latency operand 1 → 3 (address, base register):
5
Latency operand 1 → 3 (address, index register):
5
Latency operand 1 → 3 (memory):
≤7
Latency operand 2 → 1:
≤7
Latency operand 2 → 3:
1
Latency operand 3 → 1:
≤7
Latency operand 3 → 3:
1
Throughput
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 1