DIV (M16)

Experiment 1 (fast division)

Instruction: DIV word ptr [R14]
Chain instructions: MOVSX R12, AX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV AX, R8W;MOV DX, R9W
Chain latency: 11

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	4c 0f bf e0          	movsx  r12,ax
   8:	4d 31 e6             	xor    r14,r12
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	4d 31 e6             	xor    r14,r12
  20:	4d 31 e6             	xor    r14,r12
  23:	4d 31 e6             	xor    r14,r12
  26:	66 44 89 c0          	mov    ax,r8w
  2a:	66 44 89 ca          	mov    dx,r9w

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 26.38
- Reference cycles: 27.2
- UOPS_RETIRED.ALL: 18.0

Experiment 2 (slow division)

Instruction: DIV word ptr [R14]
Chain instructions: MOVSX R12, AX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV AX, R8W;MOV DX, R9W
Chain latency: 11

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	4c 0f bf e0          	movsx  r12,ax
   8:	4d 31 e6             	xor    r14,r12
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	4d 31 e6             	xor    r14,r12
  20:	4d 31 e6             	xor    r14,r12
  23:	4d 31 e6             	xor    r14,r12
  26:	66 44 89 c0          	mov    ax,r8w
  2a:	66 44 89 ca          	mov    dx,r9w

Init:

MOV R8, 133;
MOV R9, 0x343a;
MOV RCX, 0x75e6;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 33.42
- Reference cycles: 33.92
- UOPS_RETIRED.ALL: 18.0

Latency operand 1 → 2 (address, index register): 15 ≤ lat ≤ 22

Experiment 1 (fast division)

Instruction: DIV word ptr [R14]
Chain instructions: MOVSX R12, AX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV AX, R8W;MOV DX, R9W
Chain latency: 11

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	4c 0f bf e0          	movsx  r12,ax
   8:	4d 31 e6             	xor    r14,r12
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	4d 31 e6             	xor    r14,r12
  20:	4d 31 e6             	xor    r14,r12
  23:	4d 31 e6             	xor    r14,r12
  26:	66 44 89 c0          	mov    ax,r8w
  2a:	66 44 89 ca          	mov    dx,r9w

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 26.39
- Reference cycles: 27.04
- UOPS_RETIRED.ALL: 18.0

Experiment 2 (slow division)

Instruction: DIV word ptr [R14]
Chain instructions: MOVSX R12, AX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV AX, R8W;MOV DX, R9W
Chain latency: 11

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	4c 0f bf e0          	movsx  r12,ax
   8:	4d 31 e6             	xor    r14,r12
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	4d 31 e6             	xor    r14,r12
  20:	4d 31 e6             	xor    r14,r12
  23:	4d 31 e6             	xor    r14,r12
  26:	66 44 89 c0          	mov    ax,r8w
  2a:	66 44 89 ca          	mov    dx,r9w

Init:

MOV R8, 133;
MOV R9, 0x343a;
MOV RCX, 0x75e6;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 33.34
- Reference cycles: 33.92
- UOPS_RETIRED.ALL: 18.0

Latency operand 1 → 3 (address, base register): 16 ≤ lat ≤ 23

Experiment 1 (fast division)

Instruction: DIV word ptr [R14]
Chain instructions: MOVSX R12, DX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV AX, R8W;MOV DX, R9W
Chain latency: 11

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	4c 0f bf e2          	movsx  r12,dx
   8:	4d 31 e6             	xor    r14,r12
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	4d 31 e6             	xor    r14,r12
  20:	4d 31 e6             	xor    r14,r12
  23:	4d 31 e6             	xor    r14,r12
  26:	66 44 89 c0          	mov    ax,r8w
  2a:	66 44 89 ca          	mov    dx,r9w

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 27.0
- Reference cycles: 27.52
- UOPS_RETIRED.ALL: 18.0

Experiment 2 (slow division)

Instruction: DIV word ptr [R14]
Chain instructions: MOVSX R12, DX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV AX, R8W;MOV DX, R9W
Chain latency: 11

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	4c 0f bf e2          	movsx  r12,dx
   8:	4d 31 e6             	xor    r14,r12
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	4d 31 e6             	xor    r14,r12
  20:	4d 31 e6             	xor    r14,r12
  23:	4d 31 e6             	xor    r14,r12
  26:	66 44 89 c0          	mov    ax,r8w
  2a:	66 44 89 ca          	mov    dx,r9w

Init:

MOV R8, 133;
MOV R9, 0x343a;
MOV RCX, 0x75e6;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 34.0
- Reference cycles: 34.72
- UOPS_RETIRED.ALL: 18.0

Latency operand 1 → 3 (address, index register): 16 ≤ lat ≤ 23

Experiment 1 (fast division)

Instruction: DIV word ptr [R14]
Chain instructions: MOVSX R12, DX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV AX, R8W;MOV DX, R9W
Chain latency: 11

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	4c 0f bf e2          	movsx  r12,dx
   8:	4d 31 e6             	xor    r14,r12
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	4d 31 e6             	xor    r14,r12
  20:	4d 31 e6             	xor    r14,r12
  23:	4d 31 e6             	xor    r14,r12
  26:	66 44 89 c0          	mov    ax,r8w
  2a:	66 44 89 ca          	mov    dx,r9w

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 27.0
- Reference cycles: 27.68
- UOPS_RETIRED.ALL: 18.0

Experiment 2 (slow division)

Instruction: DIV word ptr [R14]
Chain instructions: MOVSX R12, DX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV AX, R8W;MOV DX, R9W
Chain latency: 11

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	4c 0f bf e2          	movsx  r12,dx
   8:	4d 31 e6             	xor    r14,r12
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	4d 31 e6             	xor    r14,r12
  20:	4d 31 e6             	xor    r14,r12
  23:	4d 31 e6             	xor    r14,r12
  26:	66 44 89 c0          	mov    ax,r8w
  2a:	66 44 89 ca          	mov    dx,r9w

Init:

MOV R8, 133;
MOV R9, 0x343a;
MOV RCX, 0x75e6;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 34.0
- Reference cycles: 34.56
- UOPS_RETIRED.ALL: 18.0

Latency operand 2 → 2: 11 ≤ lat ≤ 18

Experiment 1 (fast division)

Instruction: DIV word ptr [R14]
Chain instructions: AND AX, R8W; OR AX, R8W; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; ; MOV DX, R9W
Chain latency: 12

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	66 44 21 c0          	and    ax,r8w
   8:	66 44 09 c0          	or     ax,r8w
   c:	66 09 c0             	or     ax,ax
   f:	66 09 c0             	or     ax,ax
  12:	66 09 c0             	or     ax,ax
  15:	66 09 c0             	or     ax,ax
  18:	66 09 c0             	or     ax,ax
  1b:	66 09 c0             	or     ax,ax
  1e:	66 09 c0             	or     ax,ax
  21:	66 09 c0             	or     ax,ax
  24:	66 09 c0             	or     ax,ax
  27:	66 09 c0             	or     ax,ax
  2a:	66 44 89 ca          	mov    dx,r9w

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 23.4
- Reference cycles: 24.0
- UOPS_RETIRED.ALL: 18.0

Experiment 2 (slow division)

Instruction: DIV word ptr [R14]
Chain instructions: AND AX, R8W; OR AX, R8W; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; ; MOV DX, R9W
Chain latency: 12

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	66 44 21 c0          	and    ax,r8w
   8:	66 44 09 c0          	or     ax,r8w
   c:	66 09 c0             	or     ax,ax
   f:	66 09 c0             	or     ax,ax
  12:	66 09 c0             	or     ax,ax
  15:	66 09 c0             	or     ax,ax
  18:	66 09 c0             	or     ax,ax
  1b:	66 09 c0             	or     ax,ax
  1e:	66 09 c0             	or     ax,ax
  21:	66 09 c0             	or     ax,ax
  24:	66 09 c0             	or     ax,ax
  27:	66 09 c0             	or     ax,ax
  2a:	66 44 89 ca          	mov    dx,r9w

Init:

MOV R8, 133;
MOV R9, 0x343a;
MOV RCX, 0x75e6;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 30.4
- Reference cycles: 31.2
- UOPS_RETIRED.ALL: 18.0

Latency operand 2 → 3: 12 ≤ lat ≤ 19

Experiment 1 (fast division)

Instruction: DIV word ptr [R14]
Chain instructions: AND AX, DX; AND AX, R8W; OR AX, R8W; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; ; MOV DX, R9W
Chain latency: 13

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	66 21 d0             	and    ax,dx
   7:	66 44 21 c0          	and    ax,r8w
   b:	66 44 09 c0          	or     ax,r8w
   f:	66 09 c0             	or     ax,ax
  12:	66 09 c0             	or     ax,ax
  15:	66 09 c0             	or     ax,ax
  18:	66 09 c0             	or     ax,ax
  1b:	66 09 c0             	or     ax,ax
  1e:	66 09 c0             	or     ax,ax
  21:	66 09 c0             	or     ax,ax
  24:	66 09 c0             	or     ax,ax
  27:	66 09 c0             	or     ax,ax
  2a:	66 09 c0             	or     ax,ax
  2d:	66 44 89 ca          	mov    dx,r9w

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 25.0
- Reference cycles: 25.76
- UOPS_RETIRED.ALL: 19.0

Experiment 2 (slow division)

Instruction: DIV word ptr [R14]
Chain instructions: AND AX, DX; AND AX, R8W; OR AX, R8W; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; OR AX, AX; ; MOV DX, R9W
Chain latency: 13

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	66 21 d0             	and    ax,dx
   7:	66 44 21 c0          	and    ax,r8w
   b:	66 44 09 c0          	or     ax,r8w
   f:	66 09 c0             	or     ax,ax
  12:	66 09 c0             	or     ax,ax
  15:	66 09 c0             	or     ax,ax
  18:	66 09 c0             	or     ax,ax
  1b:	66 09 c0             	or     ax,ax
  1e:	66 09 c0             	or     ax,ax
  21:	66 09 c0             	or     ax,ax
  24:	66 09 c0             	or     ax,ax
  27:	66 09 c0             	or     ax,ax
  2a:	66 09 c0             	or     ax,ax
  2d:	66 44 89 ca          	mov    dx,r9w

Init:

MOV R8, 133;
MOV R9, 0x343a;
MOV RCX, 0x75e6;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 32.0
- Reference cycles: 32.64
- UOPS_RETIRED.ALL: 19.0

Latency operand 3 → 2: 11 ≤ lat ≤ 18

Experiment 1 (fast division)

Instruction: DIV word ptr [R14]
Chain instructions: AND DX, AX; AND DX, R9W; OR DX, R9W; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; ; MOV AX, R8W
Chain latency: 13

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	66 21 c2             	and    dx,ax
   7:	66 44 21 ca          	and    dx,r9w
   b:	66 44 09 ca          	or     dx,r9w
   f:	66 09 d2             	or     dx,dx
  12:	66 09 d2             	or     dx,dx
  15:	66 09 d2             	or     dx,dx
  18:	66 09 d2             	or     dx,dx
  1b:	66 09 d2             	or     dx,dx
  1e:	66 09 d2             	or     dx,dx
  21:	66 09 d2             	or     dx,dx
  24:	66 09 d2             	or     dx,dx
  27:	66 09 d2             	or     dx,dx
  2a:	66 09 d2             	or     dx,dx
  2d:	66 44 89 c0          	mov    ax,r8w

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 24.0
- Reference cycles: 24.96
- UOPS_RETIRED.ALL: 19.0

Experiment 2 (slow division)

Instruction: DIV word ptr [R14]
Chain instructions: AND DX, AX; AND DX, R9W; OR DX, R9W; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; ; MOV AX, R8W
Chain latency: 13

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	66 21 c2             	and    dx,ax
   7:	66 44 21 ca          	and    dx,r9w
   b:	66 44 09 ca          	or     dx,r9w
   f:	66 09 d2             	or     dx,dx
  12:	66 09 d2             	or     dx,dx
  15:	66 09 d2             	or     dx,dx
  18:	66 09 d2             	or     dx,dx
  1b:	66 09 d2             	or     dx,dx
  1e:	66 09 d2             	or     dx,dx
  21:	66 09 d2             	or     dx,dx
  24:	66 09 d2             	or     dx,dx
  27:	66 09 d2             	or     dx,dx
  2a:	66 09 d2             	or     dx,dx
  2d:	66 44 89 c0          	mov    ax,r8w

Init:

MOV R8, 133;
MOV R9, 0x343a;
MOV RCX, 0x75e6;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 31.0
- Reference cycles: 31.84
- UOPS_RETIRED.ALL: 19.0

Latency operand 3 → 3: 11 ≤ lat ≤ 18

Experiment 1 (fast division)

Instruction: DIV word ptr [R14]
Chain instructions: AND DX, R9W; OR DX, R9W; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; ; MOV AX, R8W
Chain latency: 12

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	66 44 21 ca          	and    dx,r9w
   8:	66 44 09 ca          	or     dx,r9w
   c:	66 09 d2             	or     dx,dx
   f:	66 09 d2             	or     dx,dx
  12:	66 09 d2             	or     dx,dx
  15:	66 09 d2             	or     dx,dx
  18:	66 09 d2             	or     dx,dx
  1b:	66 09 d2             	or     dx,dx
  1e:	66 09 d2             	or     dx,dx
  21:	66 09 d2             	or     dx,dx
  24:	66 09 d2             	or     dx,dx
  27:	66 09 d2             	or     dx,dx
  2a:	66 44 89 c0          	mov    ax,r8w

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 23.0
- Reference cycles: 24.0
- UOPS_RETIRED.ALL: 18.0

Experiment 2 (slow division)

Instruction: DIV word ptr [R14]
Chain instructions: AND DX, R9W; OR DX, R9W; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; OR DX, DX; ; MOV AX, R8W
Chain latency: 12

Code:

   0:	66 41 f7 36          	div    WORD PTR [r14]
   4:	66 44 21 ca          	and    dx,r9w
   8:	66 44 09 ca          	or     dx,r9w
   c:	66 09 d2             	or     dx,dx
   f:	66 09 d2             	or     dx,dx
  12:	66 09 d2             	or     dx,dx
  15:	66 09 d2             	or     dx,dx
  18:	66 09 d2             	or     dx,dx
  1b:	66 09 d2             	or     dx,dx
  1e:	66 09 d2             	or     dx,dx
  21:	66 09 d2             	or     dx,dx
  24:	66 09 d2             	or     dx,dx
  27:	66 09 d2             	or     dx,dx
  2a:	66 44 89 c0          	mov    ax,r8w

Init:

MOV R8, 133;
MOV R9, 0x343a;
MOV RCX, 0x75e6;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 30.0
- Reference cycles: 30.88
- UOPS_RETIRED.ALL: 18.0

DIV (M16) - Latency

Operands

Latency operand 1 → 2 (address, base register): 15 ≤ lat ≤ 22

Latency operand 1 → 2 (address, index register): 15 ≤ lat ≤ 22

Latency operand 1 → 3 (address, base register): 16 ≤ lat ≤ 23

Latency operand 1 → 3 (address, index register): 16 ≤ lat ≤ 23

Latency operand 2 → 2: 11 ≤ lat ≤ 18

Latency operand 2 → 3: 12 ≤ lat ≤ 19

Latency operand 3 → 2: 11 ≤ lat ≤ 18

Latency operand 3 → 3: 11 ≤ lat ≤ 18

Latency operand 1 → 2 (address, base register): 15 ≤ lat ≤ 22

Experiment 1 (fast division)

Experiment 2 (slow division)

Latency operand 1 → 2 (address, index register): 15 ≤ lat ≤ 22

Experiment 1 (fast division)

Experiment 2 (slow division)

Latency operand 1 → 3 (address, base register): 16 ≤ lat ≤ 23

Experiment 1 (fast division)

Experiment 2 (slow division)

Latency operand 1 → 3 (address, index register): 16 ≤ lat ≤ 23

Experiment 1 (fast division)

Experiment 2 (slow division)

Latency operand 2 → 2: 11 ≤ lat ≤ 18

Experiment 1 (fast division)

Experiment 2 (slow division)

Latency operand 2 → 3: 12 ≤ lat ≤ 19

Experiment 1 (fast division)

Experiment 2 (slow division)

Latency operand 3 → 2: 11 ≤ lat ≤ 18

Experiment 1 (fast division)

Experiment 2 (slow division)

Latency operand 3 → 3: 11 ≤ lat ≤ 18

Experiment 1 (fast division)

Experiment 2 (slow division)