VBLENDVPS (YMM, YMM, YMM, YMM)

Experiment 1

Instruction: VBLENDVPS YMM1, YMM0, YMM2, YMM3
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 e3 7d 4a ca 30    	vblendvps ymm1,ymm0,ymm2,ymm3
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14];
VXORPS YMM3, YMM3, YMM3

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 14.01
- Reference cycles: 14.88
- UOPS_RETIRED.ALL: 22.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPS YMM1, YMM0, YMM2, YMM3
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 e3 7d 4a ca 30    	vblendvps ymm1,ymm0,ymm2,ymm3
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14];
VXORPS YMM3, YMM3, YMM3;
VBLENDVPS YMM0, YMM1, YMM2, YMM3;
VBLENDVPS YMM2, YMM0, YMM1, YMM3;
VBLENDVPS YMM3, YMM0, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 13.94
- Reference cycles: 14.08
- UOPS_RETIRED.ALL: 22.0

Latency operand 3 → 1: 7

Experiment 1

Instruction: VBLENDVPS YMM1, YMM2, YMM0, YMM3
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 e3 6d 4a c8 30    	vblendvps ymm1,ymm2,ymm0,ymm3
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14];
VXORPS YMM3, YMM3, YMM3

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 14.17
- Reference cycles: 14.4
- UOPS_RETIRED.ALL: 22.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPS YMM1, YMM2, YMM0, YMM3
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 e3 6d 4a c8 30    	vblendvps ymm1,ymm2,ymm0,ymm3
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14];
VXORPS YMM3, YMM3, YMM3;
VBLENDVPS YMM2, YMM0, YMM1, YMM3;
VBLENDVPS YMM0, YMM1, YMM2, YMM3;
VBLENDVPS YMM3, YMM0, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 14.04
- Reference cycles: 14.24
- UOPS_RETIRED.ALL: 22.0

Latency operand 4 → 1: 6

Experiment 1

Instruction: VBLENDVPS YMM1, YMM2, YMM3, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 e3 6d 4a cb 00    	vblendvps ymm1,ymm2,ymm3,ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 13.83
- Reference cycles: 13.92
- UOPS_RETIRED.ALL: 22.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPS YMM1, YMM2, YMM3, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 e3 6d 4a cb 00    	vblendvps ymm1,ymm2,ymm3,ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VXORPS YMM0, YMM0, YMM0;
VBLENDVPS YMM2, YMM0, YMM1, YMM3;
VBLENDVPS YMM3, YMM0, YMM1, YMM2;
VBLENDVPS YMM0, YMM1, YMM2, YMM3

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 13.66
- Reference cycles: 13.92
- UOPS_RETIRED.ALL: 22.0

VBLENDVPS (YMM, YMM, YMM, YMM) - Latency

Operands

Latency operand 2 → 1: 7

Latency operand 3 → 1: 7

Latency operand 4 → 1: 6

Latency operand 2 → 1: 7

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 7

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 4 → 1: 6

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)