VCMPPS (YMM, YMM, YMM, I8)

Experiment 1

Instruction: VCMPPS YMM1, YMM0, YMM2, 2
Chain instruction: VCMPPS YMM0, YMM1, YMM2, 2

Code:

   0:	c5 fc c2 ca 02       	vcmpleps ymm1,ymm0,ymm2
   5:	c5 f4 c2 c2 02       	vcmpleps ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.99
- Reference cycles: 3.2
- UOPS_RETIRED.ALL: 4.0

Experiment 2

Instruction: VCMPPS YMM1, YMM0, YMM2, 2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c5 fc c2 ca 02       	vcmpleps ymm1,ymm0,ymm2
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.99
- Reference cycles: 9.09
- UOPS_RETIRED.ALL: 12.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VCMPPS YMM1, YMM0, YMM2, 2
Chain instruction: VCMPPS YMM0, YMM1, YMM2, 2

Code:

   0:	c5 fc c2 ca 02       	vcmpleps ymm1,ymm0,ymm2
   5:	c5 f4 c2 c2 02       	vcmpleps ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14];
VCMPPS YMM0, YMM1, YMM2, 2;
VCMPPS YMM2, YMM0, YMM1, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.93
- Reference cycles: 3.2
- UOPS_RETIRED.ALL: 4.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VCMPPS YMM1, YMM0, YMM2, 2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c5 fc c2 ca 02       	vcmpleps ymm1,ymm0,ymm2
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14];
VCMPPS YMM0, YMM1, YMM2, 2;
VCMPPS YMM2, YMM0, YMM1, 2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.93
- Reference cycles: 9.09
- UOPS_RETIRED.ALL: 12.0

Experiment 1

Instruction: VCMPPS YMM1, YMM2, YMM0, 2
Chain instruction: VCMPPS YMM0, YMM2, YMM1, 2

Code:

   0:	c5 ec c2 c8 02       	vcmpleps ymm1,ymm2,ymm0
   5:	c5 ec c2 c1 02       	vcmpleps ymm0,ymm2,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.98
- Reference cycles: 3.2
- UOPS_RETIRED.ALL: 4.0

Experiment 2

Instruction: VCMPPS YMM1, YMM2, YMM0, 2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c5 ec c2 c8 02       	vcmpleps ymm1,ymm2,ymm0
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.99
- Reference cycles: 9.26
- UOPS_RETIRED.ALL: 12.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VCMPPS YMM1, YMM2, YMM0, 2
Chain instruction: VCMPPS YMM0, YMM2, YMM1, 2

Code:

   0:	c5 ec c2 c8 02       	vcmpleps ymm1,ymm2,ymm0
   5:	c5 ec c2 c1 02       	vcmpleps ymm0,ymm2,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14];
VCMPPS YMM2, YMM0, YMM1, 2;
VCMPPS YMM0, YMM1, YMM2, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.92
- Reference cycles: 3.37
- UOPS_RETIRED.ALL: 4.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VCMPPS YMM1, YMM2, YMM0, 2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c5 ec c2 c8 02       	vcmpleps ymm1,ymm2,ymm0
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14];
VCMPPS YMM2, YMM0, YMM1, 2;
VCMPPS YMM0, YMM1, YMM2, 2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.92
- Reference cycles: 9.09
- UOPS_RETIRED.ALL: 12.0

VCMPPS (YMM, YMM, YMM, I8) - Latency

Operands

Latency operand 2 → 1: 2

Latency operand 3 → 1: 2

Latency operand 2 → 1: 2

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 2

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)