IDIV (M32) - Latency


Operands


Latency operand 1 → 2 (address, base register): 64

Latency operand 1 → 2 (address, index register): 64

Latency operand 1 → 3 (address, base register): 64

Latency operand 1 → 3 (address, index register): 64

Latency operand 2 → 2: 62

Latency operand 2 → 3: 62

Latency operand 3 → 2: 62

Latency operand 3 → 3: 62


Latency operand 1 → 2 (address, base register): 64

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 2 (address, index register): 64

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, base register): 64

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, index register): 64

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 2: 62

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 3: 62

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 2: 62

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 3: 62

Experiment 1 (fast division)

Experiment 2 (slow division)