BTR_LOCK (M32, I8)

Experiment 1

Instruction: LOCK BTR dword ptr [R14], 2
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12
Chain latency: ≥27

Code:

   0:	f0 41 0f ba 36 02    	lock btr DWORD PTR [r14],0x2
   6:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 63 e4             	movsxd r12,r12d
  1e:	4d 63 e4             	movsxd r12,r12d
  21:	4d 63 e4             	movsxd r12,r12d
  24:	4d 63 e4             	movsxd r12,r12d
  27:	4d 63 e4             	movsxd r12,r12d
  2a:	4d 63 e4             	movsxd r12,r12d
  2d:	4d 63 e4             	movsxd r12,r12d
  30:	4d 63 e4             	movsxd r12,r12d
  33:	4d 63 e4             	movsxd r12,r12d
  36:	4d 63 e4             	movsxd r12,r12d
  39:	4d 63 e4             	movsxd r12,r12d
  3c:	4d 63 e4             	movsxd r12,r12d
  3f:	4d 63 e4             	movsxd r12,r12d
  42:	4d 63 e4             	movsxd r12,r12d
  45:	4d 63 e4             	movsxd r12,r12d
  48:	4d 63 e4             	movsxd r12,r12d
  4b:	4d 63 e4             	movsxd r12,r12d
  4e:	4d 63 e4             	movsxd r12,r12d
  51:	4d 31 e6             	xor    r14,r12
  54:	4d 31 e6             	xor    r14,r12

Show nanoBench command
Results:
- Instructions retired: 28.0
- Core cycles: 56.01
- Reference cycles: 55.99
- RS_UOPS_DISPATCHED: 34.0

Experiment 2 (with additional nop)

Instruction: LOCK BTR dword ptr [R14], 2
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥27

Code:

   0:	f0 41 0f ba 36 02    	lock btr DWORD PTR [r14],0x2
   6:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 63 e4             	movsxd r12,r12d
  1e:	4d 63 e4             	movsxd r12,r12d
  21:	4d 63 e4             	movsxd r12,r12d
  24:	4d 63 e4             	movsxd r12,r12d
  27:	4d 63 e4             	movsxd r12,r12d
  2a:	4d 63 e4             	movsxd r12,r12d
  2d:	4d 63 e4             	movsxd r12,r12d
  30:	4d 63 e4             	movsxd r12,r12d
  33:	4d 63 e4             	movsxd r12,r12d
  36:	4d 63 e4             	movsxd r12,r12d
  39:	4d 63 e4             	movsxd r12,r12d
  3c:	4d 63 e4             	movsxd r12,r12d
  3f:	4d 63 e4             	movsxd r12,r12d
  42:	4d 63 e4             	movsxd r12,r12d
  45:	4d 63 e4             	movsxd r12,r12d
  48:	4d 63 e4             	movsxd r12,r12d
  4b:	4d 63 e4             	movsxd r12,r12d
  4e:	4d 63 e4             	movsxd r12,r12d
  51:	4d 31 e6             	xor    r14,r12
  54:	4d 31 e6             	xor    r14,r12
  57:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 57.0
- Reference cycles: 57.0
- RS_UOPS_DISPATCHED: 35.0

Latency operand 1 → 1 (address, index register): ≤29

Experiment 1

Instruction: LOCK BTR dword ptr [R14+R13], 2
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12
Chain latency: ≥27

Code:

   0:	f0 43 0f ba 34 2e 02 	lock btr DWORD PTR [r14+r13*1],0x2
   7:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 63 e4             	movsxd r12,r12d
  20:	4d 63 e4             	movsxd r12,r12d
  23:	4d 63 e4             	movsxd r12,r12d
  26:	4d 63 e4             	movsxd r12,r12d
  29:	4d 63 e4             	movsxd r12,r12d
  2c:	4d 63 e4             	movsxd r12,r12d
  2f:	4d 63 e4             	movsxd r12,r12d
  32:	4d 63 e4             	movsxd r12,r12d
  35:	4d 63 e4             	movsxd r12,r12d
  38:	4d 63 e4             	movsxd r12,r12d
  3b:	4d 63 e4             	movsxd r12,r12d
  3e:	4d 63 e4             	movsxd r12,r12d
  41:	4d 63 e4             	movsxd r12,r12d
  44:	4d 63 e4             	movsxd r12,r12d
  47:	4d 63 e4             	movsxd r12,r12d
  4a:	4d 63 e4             	movsxd r12,r12d
  4d:	4d 63 e4             	movsxd r12,r12d
  50:	4d 63 e4             	movsxd r12,r12d
  53:	4d 31 e5             	xor    r13,r12
  56:	4d 31 e5             	xor    r13,r12

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 28.0
- Core cycles: 56.01
- Reference cycles: 56.07
- RS_UOPS_DISPATCHED: 34.0

Experiment 2 (with additional nop)

Instruction: LOCK BTR dword ptr [R14+R13], 2
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12;nop
Chain latency: ≥27

Code:

   0:	f0 43 0f ba 34 2e 02 	lock btr DWORD PTR [r14+r13*1],0x2
   7:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 63 e4             	movsxd r12,r12d
  20:	4d 63 e4             	movsxd r12,r12d
  23:	4d 63 e4             	movsxd r12,r12d
  26:	4d 63 e4             	movsxd r12,r12d
  29:	4d 63 e4             	movsxd r12,r12d
  2c:	4d 63 e4             	movsxd r12,r12d
  2f:	4d 63 e4             	movsxd r12,r12d
  32:	4d 63 e4             	movsxd r12,r12d
  35:	4d 63 e4             	movsxd r12,r12d
  38:	4d 63 e4             	movsxd r12,r12d
  3b:	4d 63 e4             	movsxd r12,r12d
  3e:	4d 63 e4             	movsxd r12,r12d
  41:	4d 63 e4             	movsxd r12,r12d
  44:	4d 63 e4             	movsxd r12,r12d
  47:	4d 63 e4             	movsxd r12,r12d
  4a:	4d 63 e4             	movsxd r12,r12d
  4d:	4d 63 e4             	movsxd r12,r12d
  50:	4d 63 e4             	movsxd r12,r12d
  53:	4d 31 e5             	xor    r13,r12
  56:	4d 31 e5             	xor    r13,r12
  59:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 29.0
- Core cycles: 57.0
- Reference cycles: 57.04
- RS_UOPS_DISPATCHED: 35.0

Latency operand 1 → 1 (memory): 20

Experiment 1

Instruction: LOCK BTR dword ptr [R14], 2

Code:

   0:	f0 41 0f ba 36 02    	lock btr DWORD PTR [r14],0x2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 20.04
- Reference cycles: 20.04
- RS_UOPS_DISPATCHED: 7.0

Experiment 2

Instruction: LOCK BTR dword ptr [R14], 2
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOV [R14], R12D
Chain latency: 15

Code:

   0:	f0 41 0f ba 36 02    	lock btr DWORD PTR [r14],0x2
   6:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 63 e4             	movsxd r12,r12d
  1e:	4d 63 e4             	movsxd r12,r12d
  21:	4d 63 e4             	movsxd r12,r12d
  24:	4d 63 e4             	movsxd r12,r12d
  27:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 42.66
- Reference cycles: 42.63
- RS_UOPS_DISPATCHED: 20.0

Latency operand 1 → 3 (address, base register): 18

Experiment 1

Instruction: LOCK BTR dword ptr [R14], 2
Chain instruction: CMOVC R14, R14
Chain latency: 2

Code:

   0:	f0 41 0f ba 36 02    	lock btr DWORD PTR [r14],0x2
   6:	4d 0f 42 f6          	cmovb  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 20.0
- Reference cycles: 20.03
- RS_UOPS_DISPATCHED: 9.0

Experiment 2 (with dependency-breaking instructions)

Instruction: LOCK BTR dword ptr [R14], 2
Chain instructions: CMOVC R14, R14;MOV dword ptr [R14], 0
Chain latency: 2

Code:

   0:	f0 41 0f ba 36 02    	lock btr DWORD PTR [r14],0x2
   6:	4d 0f 42 f6          	cmovb  r14,r14
   a:	41 c7 06 00 00 00 00 	mov    DWORD PTR [r14],0x0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 21.0
- Reference cycles: 20.97
- RS_UOPS_DISPATCHED: 11.0

Latency operand 1 → 3 (address, index register): 18

Experiment 1

Instruction: LOCK BTR dword ptr [R14+R13], 2
Chain instruction: CMOVC R13, R13
Chain latency: 2

Code:

   0:	f0 43 0f ba 34 2e 02 	lock btr DWORD PTR [r14+r13*1],0x2
   7:	4d 0f 42 ed          	cmovb  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 20.01
- Reference cycles: 20.01
- RS_UOPS_DISPATCHED: 9.0

Experiment 2 (with dependency-breaking instructions)

Instruction: LOCK BTR dword ptr [R14+R13], 2
Chain instructions: CMOVC R13, R13;MOV dword ptr [R14], 0
Chain latency: 2

Code:

   0:	f0 43 0f ba 34 2e 02 	lock btr DWORD PTR [r14+r13*1],0x2
   7:	4d 0f 42 ed          	cmovb  r13,r13
   b:	41 c7 06 00 00 00 00 	mov    DWORD PTR [r14],0x0

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 21.0
- Reference cycles: 21.0
- RS_UOPS_DISPATCHED: 11.0

Latency operand 1 → 3 (memory): ≤13

Experiment 1

Instruction: LOCK BTR dword ptr [R14], 2
Chain instructions: CMOVC R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥27

Code:

   0:	f0 41 0f ba 36 02    	lock btr DWORD PTR [r14],0x2
   6:	4d 0f 42 e4          	cmovb  r12,r12
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 63 e4             	movsxd r12,r12d
  1c:	4d 63 e4             	movsxd r12,r12d
  1f:	4d 63 e4             	movsxd r12,r12d
  22:	4d 63 e4             	movsxd r12,r12d
  25:	4d 63 e4             	movsxd r12,r12d
  28:	4d 63 e4             	movsxd r12,r12d
  2b:	4d 63 e4             	movsxd r12,r12d
  2e:	4d 63 e4             	movsxd r12,r12d
  31:	4d 63 e4             	movsxd r12,r12d
  34:	4d 63 e4             	movsxd r12,r12d
  37:	4d 63 e4             	movsxd r12,r12d
  3a:	4d 63 e4             	movsxd r12,r12d
  3d:	4d 63 e4             	movsxd r12,r12d
  40:	4d 63 e4             	movsxd r12,r12d
  43:	4d 63 e4             	movsxd r12,r12d
  46:	4d 63 e4             	movsxd r12,r12d
  49:	4d 63 e4             	movsxd r12,r12d
  4c:	4d 63 e4             	movsxd r12,r12d
  4f:	4d 63 e4             	movsxd r12,r12d
  52:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 27.0
- Core cycles: 40.63
- Reference cycles: 40.63
- RS_UOPS_DISPATCHED: 35.0

BTR_LOCK (M32, I8) - Latency

Operands

Latency operand 1 → 1 (address, base register): ≤29

Latency operand 1 → 1 (address, index register): ≤29

Latency operand 1 → 1 (memory): 20

Latency operand 1 → 3 (address, base register): 18

Latency operand 1 → 3 (address, index register): 18

Latency operand 1 → 3 (memory): ≤13

Latency operand 1 → 1 (address, base register): ≤29

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (address, index register): ≤29

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (memory): 20

Experiment 1

Experiment 2

Latency operand 1 → 3 (address, base register): 18

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Latency operand 1 → 3 (address, index register): 18

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Latency operand 1 → 3 (memory): ≤13

Experiment 1