CVTSI2SS (XMM, R32)

Experiment 1

Instruction: CVTSI2SS XMM0, R8D

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 2.99
- RS_UOPS_DISPATCHED: 1.0

Experiment 2

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.0
- Reference cycles: 10.01
- RS_UOPS_DISPATCHED: 8.0

Experiment 3

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 10

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 13.0
- Reference cycles: 12.99
- RS_UOPS_DISPATCHED: 9.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: CVTSI2SS XMM0, R8D

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 2.99
- RS_UOPS_DISPATCHED: 1.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.0
- Reference cycles: 10.0
- RS_UOPS_DISPATCHED: 8.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 10

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 13.0
- Reference cycles: 12.96
- RS_UOPS_DISPATCHED: 9.0

Experiment 1

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: CVTSS2SI R8D, XMM0
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 44 0f 2d c0       	cvtss2si r8d,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 6.04
- RS_UOPS_DISPATCHED: 2.0

Experiment 2 (with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: CVTSS2SI R8D, XMM0;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 44 0f 2d c0       	cvtss2si r8d,xmm0
   a:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.0
- Reference cycles: 6.01
- RS_UOPS_DISPATCHED: 3.0

Experiment 3

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: CVTSS2SI R8, XMM0
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 4c 0f 2d c0       	cvtss2si r8,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 7.0
- Reference cycles: 7.03
- RS_UOPS_DISPATCHED: 3.0

Experiment 4 (with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: CVTSS2SI R8, XMM0;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 4c 0f 2d c0       	cvtss2si r8,xmm0
   a:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 7.0
- Reference cycles: 6.97
- RS_UOPS_DISPATCHED: 4.0

Experiment 5

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: CVTTSS2SI R8D, XMM0
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 44 0f 2c c0       	cvttss2si r8d,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 5.97
- RS_UOPS_DISPATCHED: 2.0

Experiment 6 (with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: CVTTSS2SI R8D, XMM0;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 44 0f 2c c0       	cvttss2si r8d,xmm0
   a:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.0
- Reference cycles: 5.97
- RS_UOPS_DISPATCHED: 3.0

Experiment 7

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: CVTTSS2SI R8, XMM0
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 4c 0f 2c c0       	cvttss2si r8,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 7.0
- Reference cycles: 7.0
- RS_UOPS_DISPATCHED: 3.0

Experiment 8 (with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: CVTTSS2SI R8, XMM0;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 4c 0f 2c c0       	cvttss2si r8,xmm0
   a:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 7.0
- Reference cycles: 6.97
- RS_UOPS_DISPATCHED: 4.0

Experiment 9

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: MOVD R8D, XMM0
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 41 0f 7e c0       	movd   r8d,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 6.0
- RS_UOPS_DISPATCHED: 2.0

Experiment 10 (with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: MOVD R8D, XMM0;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 41 0f 7e c0       	movd   r8d,xmm0
   a:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.0
- Reference cycles: 5.97
- RS_UOPS_DISPATCHED: 3.0

Experiment 11

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: MOVQ R8, XMM0
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 49 0f 7e c0       	movq   r8,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 6.0
- RS_UOPS_DISPATCHED: 2.0

Experiment 12 (with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: MOVQ R8, XMM0;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 49 0f 7e c0       	movq   r8,xmm0
   a:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.0
- Reference cycles: 5.97
- RS_UOPS_DISPATCHED: 3.0

Experiment 13

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: PEXTRW R8D, XMM0, 2
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 44 0f c5 c0 02    	pextrw r8d,xmm0,0x2

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 10.01
- Reference cycles: 10.01
- RS_UOPS_DISPATCHED: 4.0

Experiment 14 (with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: PEXTRW R8D, XMM0, 2;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 44 0f c5 c0 02    	pextrw r8d,xmm0,0x2
   b:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 10.01
- Reference cycles: 9.99
- RS_UOPS_DISPATCHED: 5.0

Experiment 15

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: PMOVMSKB R8D, XMM0
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 44 0f d7 c0       	pmovmskb r8d,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.0
- Reference cycles: 3.97
- RS_UOPS_DISPATCHED: 2.0

Experiment 16 (with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: PMOVMSKB R8D, XMM0;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 44 0f d7 c0       	pmovmskb r8d,xmm0
   a:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.0
- Reference cycles: 3.97
- RS_UOPS_DISPATCHED: 3.0

Experiment 17 (source registers initialized by an instruction of the same kind)

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: CVTSS2SI R8D, XMM0
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 44 0f 2d c0       	cvtss2si r8d,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 5.92
- RS_UOPS_DISPATCHED: 2.0

Experiment 18 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: CVTSS2SI R8D, XMM0;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 44 0f 2d c0       	cvtss2si r8d,xmm0
   a:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.0
- Reference cycles: 6.01
- RS_UOPS_DISPATCHED: 3.0

Experiment 19 (source registers initialized by an instruction of the same kind)

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: CVTSS2SI R8, XMM0
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 4c 0f 2d c0       	cvtss2si r8,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 7.0
- Reference cycles: 7.04
- RS_UOPS_DISPATCHED: 3.0

Experiment 20 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: CVTSS2SI R8, XMM0;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 4c 0f 2d c0       	cvtss2si r8,xmm0
   a:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 7.0
- Reference cycles: 7.0
- RS_UOPS_DISPATCHED: 4.0

Experiment 21 (source registers initialized by an instruction of the same kind)

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: CVTTSS2SI R8D, XMM0
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 44 0f 2c c0       	cvttss2si r8d,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 6.0
- RS_UOPS_DISPATCHED: 2.0

Experiment 22 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: CVTTSS2SI R8D, XMM0;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 44 0f 2c c0       	cvttss2si r8d,xmm0
   a:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.0
- Reference cycles: 6.01
- RS_UOPS_DISPATCHED: 3.0

Experiment 23 (source registers initialized by an instruction of the same kind)

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: CVTTSS2SI R8, XMM0
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 4c 0f 2c c0       	cvttss2si r8,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 7.0
- Reference cycles: 7.04
- RS_UOPS_DISPATCHED: 3.0

Experiment 24 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: CVTTSS2SI R8, XMM0;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	f3 4c 0f 2c c0       	cvttss2si r8,xmm0
   a:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 7.0
- Reference cycles: 6.97
- RS_UOPS_DISPATCHED: 4.0

Experiment 25 (source registers initialized by an instruction of the same kind)

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: MOVD R8D, XMM0
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 41 0f 7e c0       	movd   r8d,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 6.0
- RS_UOPS_DISPATCHED: 2.0

Experiment 26 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: MOVD R8D, XMM0;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 41 0f 7e c0       	movd   r8d,xmm0
   a:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.0
- Reference cycles: 6.01
- RS_UOPS_DISPATCHED: 3.0

Experiment 27 (source registers initialized by an instruction of the same kind)

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: MOVQ R8, XMM0
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 49 0f 7e c0       	movq   r8,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 6.0
- RS_UOPS_DISPATCHED: 2.0

Experiment 28 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: MOVQ R8, XMM0;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 49 0f 7e c0       	movq   r8,xmm0
   a:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.0
- Reference cycles: 6.01
- RS_UOPS_DISPATCHED: 3.0

Experiment 29 (source registers initialized by an instruction of the same kind)

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: PEXTRW R8D, XMM0, 2
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 44 0f c5 c0 02    	pextrw r8d,xmm0,0x2

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 10.01
- Reference cycles: 10.0
- RS_UOPS_DISPATCHED: 4.0

Experiment 30 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: PEXTRW R8D, XMM0, 2;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 44 0f c5 c0 02    	pextrw r8d,xmm0,0x2
   b:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 10.01
- Reference cycles: 10.01
- RS_UOPS_DISPATCHED: 5.0

Experiment 31 (source registers initialized by an instruction of the same kind)

Instruction: CVTSI2SS XMM0, R8D
Chain instruction: PMOVMSKB R8D, XMM0
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 44 0f d7 c0       	pmovmskb r8d,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.0
- Reference cycles: 4.0
- RS_UOPS_DISPATCHED: 2.0

Experiment 32 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: CVTSI2SS XMM0, R8D
Chain instructions: PMOVMSKB R8D, XMM0;MOVUPD XMM0, XMM15
Chain latency: ≥1

Code:

   0:	f3 41 0f 2a c0       	cvtsi2ss xmm0,r8d
   5:	66 44 0f d7 c0       	pmovmskb r8d,xmm0
   a:	66 41 0f 10 c7       	movupd xmm0,xmm15

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
CVTSI2SS XMM0, R8D

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.0
- Reference cycles: 4.01
- RS_UOPS_DISPATCHED: 3.0

CVTSI2SS (XMM, R32) - Latency

Operands

Latency operand 1 → 1: 3

Latency operand 2 → 1: ≤3

Latency operand 1 → 1: 3

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: ≤3

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5

Experiment 6 (with dependency-breaking instructions)

Experiment 7

Experiment 8 (with dependency-breaking instructions)

Experiment 9

Experiment 10 (with dependency-breaking instructions)

Experiment 11

Experiment 12 (with dependency-breaking instructions)

Experiment 13

Experiment 14 (with dependency-breaking instructions)

Experiment 15

Experiment 16 (with dependency-breaking instructions)

Experiment 17 (source registers initialized by an instruction of the same kind)

Experiment 18 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 19 (source registers initialized by an instruction of the same kind)

Experiment 20 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 21 (source registers initialized by an instruction of the same kind)

Experiment 22 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 23 (source registers initialized by an instruction of the same kind)

Experiment 24 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 25 (source registers initialized by an instruction of the same kind)

Experiment 26 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 27 (source registers initialized by an instruction of the same kind)

Experiment 28 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 29 (source registers initialized by an instruction of the same kind)

Experiment 30 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 31 (source registers initialized by an instruction of the same kind)

Experiment 32 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)