ADD (M32, R32)

Experiment 1 (with R8D=0)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   6:	4d 63 e4             	movsxd r12,r12d
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12

Init:
```
MOV R8D, 0
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 9.35
- Reference cycles: 7.28
- UOPS_RETIRED.ALL: 8.0

Experiment 2 (with R8D=1)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   6:	4d 63 e4             	movsxd r12,r12d
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12

Init:
```
MOV R8D, 1
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 9.36
- Reference cycles: 7.28
- UOPS_RETIRED.ALL: 8.0

Experiment 3 (with R8D=2)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   6:	4d 63 e4             	movsxd r12,r12d
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12

Init:
```
MOV R8D, 2
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 9.42
- Reference cycles: 7.54
- UOPS_RETIRED.ALL: 8.0

Experiment 4 (with additional nop, with R8D=0)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   6:	4d 63 e4             	movsxd r12,r12d
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12
  18:	90                   	nop

Init:
```
MOV R8D, 0
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.16
- Reference cycles: 9.1
- UOPS_RETIRED.ALL: 9.0

Experiment 5 (with additional nop, with R8D=1)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   6:	4d 63 e4             	movsxd r12,r12d
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12
  18:	90                   	nop

Init:
```
MOV R8D, 1
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 10.81
- Reference cycles: 8.58
- UOPS_RETIRED.ALL: 9.0

Experiment 6 (with additional nop, with R8D=2)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   6:	4d 63 e4             	movsxd r12,r12d
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12
  18:	90                   	nop

Init:
```
MOV R8D, 2
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.2
- Reference cycles: 9.1
- UOPS_RETIRED.ALL: 9.0

Latency operand 1 → 1 (address, index register): ≤3

Experiment 1

Instruction: ADD dword ptr [R14+R13], R8D
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12
Chain latency: ≥6

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 31 e5             	xor    r13,r12
  17:	4d 31 e5             	xor    r13,r12

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 9.7
- Reference cycles: 7.8
- UOPS_RETIRED.ALL: 8.0

Experiment 2 (with additional nop)

Instruction: ADD dword ptr [R14+R13], R8D
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12;nop
Chain latency: ≥6

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 31 e5             	xor    r13,r12
  17:	4d 31 e5             	xor    r13,r12
  1a:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 9.79
- Reference cycles: 7.8
- UOPS_RETIRED.ALL: 9.0

Experiment 3 (with clean upper 32 bits)

Instruction: ADD dword ptr [R14+R13], R8D
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12
Chain latency: ≥6

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 31 e5             	xor    r13,r12
  17:	4d 31 e5             	xor    r13,r12

Init:
```
XOR R13, R13;
MOV R8D, R8D;
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 9.68
- Reference cycles: 7.8
- UOPS_RETIRED.ALL: 8.0

Experiment 4 (with additional nop, with clean upper 32 bits)

Instruction: ADD dword ptr [R14+R13], R8D
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12;nop
Chain latency: ≥6

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 31 e5             	xor    r13,r12
  17:	4d 31 e5             	xor    r13,r12
  1a:	90                   	nop

Init:
```
XOR R13, R13;
MOV R8D, R8D;
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 10.08
- Reference cycles: 7.93
- UOPS_RETIRED.ALL: 9.0

Latency operand 1 → 1 (memory): 1

Experiment 1 (with R8D=0)

Instruction: ADD dword ptr [R14], R8D

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d

Init:
```
MOV R8D, 0
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.99
- Reference cycles: 0.39
- UOPS_RETIRED.ALL: 1.0

Experiment 2 (with R8D=1)

Instruction: ADD dword ptr [R14], R8D

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d

Init:
```
MOV R8D, 1
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.04
- UOPS_RETIRED.ALL: 1.0

Experiment 3 (with R8D=2)

Instruction: ADD dword ptr [R14], R8D

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d

Init:
```
MOV R8D, 2
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.17
- UOPS_RETIRED.ALL: 1.0

Experiment 4 (with R8D=0)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOV [R14], R12D
Chain latency: 10

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   6:	4d 63 e4             	movsxd r12,r12d
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 63 e4             	movsxd r12,r12d
  1e:	4d 63 e4             	movsxd r12,r12d
  21:	4d 63 e4             	movsxd r12,r12d
  24:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 0
```
Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 10.99
- Reference cycles: 8.71
- UOPS_RETIRED.ALL: 13.0

Experiment 5 (with R8D=1)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOV [R14], R12D
Chain latency: 10

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   6:	4d 63 e4             	movsxd r12,r12d
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 63 e4             	movsxd r12,r12d
  1e:	4d 63 e4             	movsxd r12,r12d
  21:	4d 63 e4             	movsxd r12,r12d
  24:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 1
```
Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 11.0
- Reference cycles: 8.45
- UOPS_RETIRED.ALL: 13.0

Experiment 6 (with R8D=2)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOV [R14], R12D
Chain latency: 10

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   6:	4d 63 e4             	movsxd r12,r12d
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 63 e4             	movsxd r12,r12d
  1e:	4d 63 e4             	movsxd r12,r12d
  21:	4d 63 e4             	movsxd r12,r12d
  24:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 2
```
Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 11.0
- Reference cycles: 8.84
- UOPS_RETIRED.ALL: 13.0

Latency operand 1 → 3 (address, base register): 0

Experiment 1 (with R8D=0)

Instruction: ADD dword ptr [R14], R8D
Chain instruction: CMOVC R14, R14
Chain latency: 2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 42 f6          	cmovb  r14,r14

Init:
```
MOV R8D, 0
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.43
- UOPS_RETIRED.ALL: 2.0

Experiment 2 (with R8D=1)

Instruction: ADD dword ptr [R14], R8D
Chain instruction: CMOVC R14, R14
Chain latency: 2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 42 f6          	cmovb  r14,r14

Init:
```
MOV R8D, 1
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.99
- Reference cycles: 1.69
- UOPS_RETIRED.ALL: 2.0

Experiment 3 (with R8D=2)

Instruction: ADD dword ptr [R14], R8D
Chain instruction: CMOVC R14, R14
Chain latency: 2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 42 f6          	cmovb  r14,r14

Init:
```
MOV R8D, 2
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.99
- Reference cycles: 1.43
- UOPS_RETIRED.ALL: 2.0

Experiment 4 (with R8D=0)

Instruction: ADD dword ptr [R14], R8D
Chain instruction: CMOVS R14, R14
Chain latency: 2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 48 f6          	cmovs  r14,r14

Init:
```
MOV R8D, 0
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.56
- UOPS_RETIRED.ALL: 2.0

Experiment 5 (with R8D=1)

Instruction: ADD dword ptr [R14], R8D
Chain instruction: CMOVS R14, R14
Chain latency: 2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 48 f6          	cmovs  r14,r14

Init:
```
MOV R8D, 1
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.99
- Reference cycles: 1.43
- UOPS_RETIRED.ALL: 2.0

Experiment 6 (with R8D=2)

Instruction: ADD dword ptr [R14], R8D
Chain instruction: CMOVS R14, R14
Chain latency: 2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 48 f6          	cmovs  r14,r14

Init:
```
MOV R8D, 2
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.82
- UOPS_RETIRED.ALL: 2.0

Experiment 7 (with R8D=0)

Instruction: ADD dword ptr [R14], R8D
Chain instruction: CMOVZ R14, R14
Chain latency: 2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 44 f6          	cmove  r14,r14

Init:
```
MOV R8D, 0
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.99
- Reference cycles: 1.69
- UOPS_RETIRED.ALL: 2.0

Experiment 8 (with R8D=1)

Instruction: ADD dword ptr [R14], R8D
Chain instruction: CMOVZ R14, R14
Chain latency: 2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 44 f6          	cmove  r14,r14

Init:
```
MOV R8D, 1
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.43
- UOPS_RETIRED.ALL: 2.0

Experiment 9 (with R8D=2)

Instruction: ADD dword ptr [R14], R8D
Chain instruction: CMOVZ R14, R14
Chain latency: 2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 44 f6          	cmove  r14,r14

Init:
```
MOV R8D, 2
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.99
- Reference cycles: 1.43
- UOPS_RETIRED.ALL: 2.0

Experiment 10 (with R8D=0)

Instruction: ADD dword ptr [R14], R8D
Chain instruction: CMOVO R14, R14
Chain latency: 2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 40 f6          	cmovo  r14,r14

Init:
```
MOV R8D, 0
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.99
- Reference cycles: 1.69
- UOPS_RETIRED.ALL: 2.0

Experiment 11 (with R8D=1)

Instruction: ADD dword ptr [R14], R8D
Chain instruction: CMOVO R14, R14
Chain latency: 2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 40 f6          	cmovo  r14,r14

Init:
```
MOV R8D, 1
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.56
- UOPS_RETIRED.ALL: 2.0

Experiment 12 (with R8D=2)

Instruction: ADD dword ptr [R14], R8D
Chain instruction: CMOVO R14, R14
Chain latency: 2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 40 f6          	cmovo  r14,r14

Init:
```
MOV R8D, 2
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.69
- UOPS_RETIRED.ALL: 2.0

Experiment 13 (with R8D=0)

Instruction: ADD dword ptr [R14], R8D
Chain instruction: CMOVP R14, R14
Chain latency: 2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 4a f6          	cmovp  r14,r14

Init:
```
MOV R8D, 0
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.99
- Reference cycles: 1.17
- UOPS_RETIRED.ALL: 2.0

Experiment 14 (with R8D=1)

Instruction: ADD dword ptr [R14], R8D
Chain instruction: CMOVP R14, R14
Chain latency: 2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 4a f6          	cmovp  r14,r14

Init:
```
MOV R8D, 1
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.56
- UOPS_RETIRED.ALL: 2.0

Experiment 15 (with R8D=2)

Instruction: ADD dword ptr [R14], R8D
Chain instruction: CMOVP R14, R14
Chain latency: 2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 4a f6          	cmovp  r14,r14

Init:
```
MOV R8D, 2
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.99
- Reference cycles: 1.69
- UOPS_RETIRED.ALL: 2.0

Latency operand 1 → 3 (address, index register): 0

Experiment 1

Instruction: ADD dword ptr [R14+R13], R8D
Chain instruction: CMOVC R13, R13
Chain latency: 2

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	4d 0f 42 ed          	cmovb  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.56
- UOPS_RETIRED.ALL: 2.0

Experiment 2

Instruction: ADD dword ptr [R14+R13], R8D
Chain instruction: CMOVS R13, R13
Chain latency: 2

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	4d 0f 48 ed          	cmovs  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.43
- UOPS_RETIRED.ALL: 2.0

Experiment 3

Instruction: ADD dword ptr [R14+R13], R8D
Chain instruction: CMOVZ R13, R13
Chain latency: 2

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	4d 0f 44 ed          	cmove  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.69
- UOPS_RETIRED.ALL: 2.0

Experiment 4

Instruction: ADD dword ptr [R14+R13], R8D
Chain instruction: CMOVO R13, R13
Chain latency: 2

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	4d 0f 40 ed          	cmovo  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.56
- UOPS_RETIRED.ALL: 2.0

Experiment 5

Instruction: ADD dword ptr [R14+R13], R8D
Chain instruction: CMOVP R13, R13
Chain latency: 2

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	4d 0f 4a ed          	cmovp  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.3
- UOPS_RETIRED.ALL: 2.0

Experiment 6 (with clean upper 32 bits)

Instruction: ADD dword ptr [R14+R13], R8D
Chain instruction: CMOVC R13, R13
Chain latency: 2

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	4d 0f 42 ed          	cmovb  r13,r13

Init:
```
XOR R13, R13;
MOV R8D, R8D;
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.99
- Reference cycles: 1.69
- UOPS_RETIRED.ALL: 2.0

Experiment 7 (with clean upper 32 bits)

Instruction: ADD dword ptr [R14+R13], R8D
Chain instruction: CMOVS R13, R13
Chain latency: 2

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	4d 0f 48 ed          	cmovs  r13,r13

Init:
```
XOR R13, R13;
MOV R8D, R8D;
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.69
- UOPS_RETIRED.ALL: 2.0

Experiment 8 (with clean upper 32 bits)

Instruction: ADD dword ptr [R14+R13], R8D
Chain instruction: CMOVZ R13, R13
Chain latency: 2

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	4d 0f 44 ed          	cmove  r13,r13

Init:
```
XOR R13, R13;
MOV R8D, R8D;
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.43
- UOPS_RETIRED.ALL: 2.0

Experiment 9 (with clean upper 32 bits)

Instruction: ADD dword ptr [R14+R13], R8D
Chain instruction: CMOVO R13, R13
Chain latency: 2

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	4d 0f 40 ed          	cmovo  r13,r13

Init:
```
XOR R13, R13;
MOV R8D, R8D;
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.69
- UOPS_RETIRED.ALL: 2.0

Experiment 10 (with clean upper 32 bits)

Instruction: ADD dword ptr [R14+R13], R8D
Chain instruction: CMOVP R13, R13
Chain latency: 2

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	4d 0f 4a ed          	cmovp  r13,r13

Init:
```
XOR R13, R13;
MOV R8D, R8D;
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.43
- UOPS_RETIRED.ALL: 2.0

Latency operand 1 → 3 (memory): ≤1

Experiment 1 (with R8D=0)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVC R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 42 e4          	cmovb  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 0
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.03
- Reference cycles: 5.72
- UOPS_RETIRED.ALL: 7.0

Experiment 2 (with R8D=1)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVC R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 42 e4          	cmovb  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 1
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.09
- Reference cycles: 5.59
- UOPS_RETIRED.ALL: 7.0

Experiment 3 (with R8D=2)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVC R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 42 e4          	cmovb  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 2
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.09
- Reference cycles: 5.33
- UOPS_RETIRED.ALL: 7.0

Experiment 4 (with R8D=0)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVS R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 48 e4          	cmovs  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 0
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.08
- Reference cycles: 6.11
- UOPS_RETIRED.ALL: 7.0

Experiment 5 (with R8D=1)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVS R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 48 e4          	cmovs  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 1
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.09
- Reference cycles: 5.59
- UOPS_RETIRED.ALL: 7.0

Experiment 6 (with R8D=2)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVS R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 48 e4          	cmovs  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 2
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.04
- Reference cycles: 5.72
- UOPS_RETIRED.ALL: 7.0

Experiment 7 (with R8D=0)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVZ R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 44 e4          	cmove  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 0
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.08
- Reference cycles: 5.59
- UOPS_RETIRED.ALL: 7.0

Experiment 8 (with R8D=1)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVZ R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 44 e4          	cmove  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 1
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.08
- Reference cycles: 5.59
- UOPS_RETIRED.ALL: 7.0

Experiment 9 (with R8D=2)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVZ R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 44 e4          	cmove  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 2
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.09
- Reference cycles: 5.98
- UOPS_RETIRED.ALL: 7.0

Experiment 10 (with R8D=0)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVO R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 40 e4          	cmovo  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 0
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.08
- Reference cycles: 5.59
- UOPS_RETIRED.ALL: 7.0

Experiment 11 (with R8D=1)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVO R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 40 e4          	cmovo  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 1
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.08
- Reference cycles: 5.59
- UOPS_RETIRED.ALL: 7.0

Experiment 12 (with R8D=2)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVO R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 40 e4          	cmovo  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 2
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.09
- Reference cycles: 5.46
- UOPS_RETIRED.ALL: 7.0

Experiment 13 (with R8D=0)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVP R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 4a e4          	cmovp  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 0
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.09
- Reference cycles: 5.46
- UOPS_RETIRED.ALL: 7.0

Experiment 14 (with R8D=1)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVP R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 4a e4          	cmovp  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 1
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.0
- Reference cycles: 5.72
- UOPS_RETIRED.ALL: 7.0

Experiment 15 (with R8D=2)

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVP R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥6

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	4d 0f 4a e4          	cmovp  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	45 89 26             	mov    DWORD PTR [r14],r12d

Init:
```
MOV R8D, 2
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.01
- Reference cycles: 5.59
- UOPS_RETIRED.ALL: 7.0

Latency operand 2 → 1: ≤1

Latency operand 2 → 3: 1

Experiment 1

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVC R15D, R15D;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 7

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 0f 42 ff          	cmovb  r15d,r15d
   7:	4d 63 c7             	movsxd r8,r15d
   a:	4d 63 c0             	movsxd r8,r8d
   d:	4d 63 c0             	movsxd r8,r8d
  10:	4d 63 c0             	movsxd r8,r8d
  13:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 8.0
- Reference cycles: 6.11
- UOPS_RETIRED.ALL: 7.0

Experiment 2

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVS R15D, R15D;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 7

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 0f 48 ff          	cmovs  r15d,r15d
   7:	4d 63 c7             	movsxd r8,r15d
   a:	4d 63 c0             	movsxd r8,r8d
   d:	4d 63 c0             	movsxd r8,r8d
  10:	4d 63 c0             	movsxd r8,r8d
  13:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 8.02
- Reference cycles: 6.37
- UOPS_RETIRED.ALL: 7.0

Experiment 3

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVZ R15D, R15D;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 7

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 0f 44 ff          	cmove  r15d,r15d
   7:	4d 63 c7             	movsxd r8,r15d
   a:	4d 63 c0             	movsxd r8,r8d
   d:	4d 63 c0             	movsxd r8,r8d
  10:	4d 63 c0             	movsxd r8,r8d
  13:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.98
- Reference cycles: 6.63
- UOPS_RETIRED.ALL: 7.0

Experiment 4

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVO R15D, R15D;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 7

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 0f 40 ff          	cmovo  r15d,r15d
   7:	4d 63 c7             	movsxd r8,r15d
   a:	4d 63 c0             	movsxd r8,r8d
   d:	4d 63 c0             	movsxd r8,r8d
  10:	4d 63 c0             	movsxd r8,r8d
  13:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.97
- Reference cycles: 6.37
- UOPS_RETIRED.ALL: 7.0

Experiment 5

Instruction: ADD dword ptr [R14], R8D
Chain instructions: CMOVP R15D, R15D;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 7

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 0f 4a ff          	cmovp  r15d,r15d
   7:	4d 63 c7             	movsxd r8,r15d
   a:	4d 63 c0             	movsxd r8,r8d
   d:	4d 63 c0             	movsxd r8,r8d
  10:	4d 63 c0             	movsxd r8,r8d
  13:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 8.0
- Reference cycles: 6.5
- UOPS_RETIRED.ALL: 7.0

ADD (M32, R32) - Latency

Operands

Latency operand 1 → 1 (address, base register): ≤3

Latency operand 1 → 1 (address, index register): ≤3

Latency operand 1 → 1 (memory): 1

Latency operand 1 → 3 (address, base register): 0

Latency operand 1 → 3 (address, index register): 0

Latency operand 1 → 3 (memory): ≤1

Latency operand 2 → 1: ≤1

Latency operand 2 → 3: 1

Latency operand 1 → 1 (address, base register): ≤3

Experiment 1 (with R8D=0)

Experiment 2 (with R8D=1)

Experiment 3 (with R8D=2)

Experiment 4 (with additional nop, with R8D=0)

Experiment 5 (with additional nop, with R8D=1)

Experiment 6 (with additional nop, with R8D=2)

Latency operand 1 → 1 (address, index register): ≤3

Experiment 1

Experiment 2 (with additional nop)

Experiment 3 (with clean upper 32 bits)

Experiment 4 (with additional nop, with clean upper 32 bits)

Latency operand 1 → 1 (memory): 1

Experiment 1 (with R8D=0)

Experiment 2 (with R8D=1)

Experiment 3 (with R8D=2)

Experiment 4 (with R8D=0)

Experiment 5 (with R8D=1)

Experiment 6 (with R8D=2)

Latency operand 1 → 3 (address, base register): 0

Experiment 1 (with R8D=0)

Experiment 2 (with R8D=1)

Experiment 3 (with R8D=2)

Experiment 4 (with R8D=0)

Experiment 5 (with R8D=1)

Experiment 6 (with R8D=2)

Experiment 7 (with R8D=0)

Experiment 8 (with R8D=1)

Experiment 9 (with R8D=2)

Experiment 10 (with R8D=0)

Experiment 11 (with R8D=1)

Experiment 12 (with R8D=2)

Experiment 13 (with R8D=0)

Experiment 14 (with R8D=1)

Experiment 15 (with R8D=2)

Latency operand 1 → 3 (address, index register): 0

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Experiment 6 (with clean upper 32 bits)

Experiment 7 (with clean upper 32 bits)

Experiment 8 (with clean upper 32 bits)

Experiment 9 (with clean upper 32 bits)

Experiment 10 (with clean upper 32 bits)

Latency operand 1 → 3 (memory): ≤1

Experiment 1 (with R8D=0)

Experiment 2 (with R8D=1)

Experiment 3 (with R8D=2)

Experiment 4 (with R8D=0)

Experiment 5 (with R8D=1)

Experiment 6 (with R8D=2)

Experiment 7 (with R8D=0)

Experiment 8 (with R8D=1)

Experiment 9 (with R8D=2)

Experiment 10 (with R8D=0)

Experiment 11 (with R8D=1)

Experiment 12 (with R8D=2)

Experiment 13 (with R8D=0)

Experiment 14 (with R8D=1)

Experiment 15 (with R8D=2)

Latency operand 2 → 1: ≤1

Experiment 1

Latency operand 2 → 3: 1

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5