VSHUFPS (XMM, XMM, XMM, I8)

Experiment 1

Instruction: VSHUFPS XMM1, XMM0, XMM2, 2
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c5 f8 c6 ca 02       	vshufps xmm1,xmm0,xmm2,0x2
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2

Instruction: VSHUFPS XMM1, XMM0, XMM2, 2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c5 f8 c6 ca 02       	vshufps xmm1,xmm0,xmm2,0x2
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VSHUFPS XMM1, XMM0, XMM2, 2
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c5 f8 c6 ca 02       	vshufps xmm1,xmm0,xmm2,0x2
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14];
VSHUFPS XMM0, XMM1, XMM2, 2;
VSHUFPS XMM2, XMM0, XMM1, 2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VSHUFPS XMM1, XMM0, XMM2, 2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c5 f8 c6 ca 02       	vshufps xmm1,xmm0,xmm2,0x2
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14];
VSHUFPS XMM0, XMM1, XMM2, 2;
VSHUFPS XMM2, XMM0, XMM1, 2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 6.0

Experiment 1

Instruction: VSHUFPS XMM1, XMM2, XMM0, 2
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c5 e8 c6 c8 02       	vshufps xmm1,xmm2,xmm0,0x2
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2

Instruction: VSHUFPS XMM1, XMM2, XMM0, 2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c5 e8 c6 c8 02       	vshufps xmm1,xmm2,xmm0,0x2
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VSHUFPS XMM1, XMM2, XMM0, 2
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c5 e8 c6 c8 02       	vshufps xmm1,xmm2,xmm0,0x2
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14];
VSHUFPS XMM2, XMM0, XMM1, 2;
VSHUFPS XMM0, XMM1, XMM2, 2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VSHUFPS XMM1, XMM2, XMM0, 2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c5 e8 c6 c8 02       	vshufps xmm1,xmm2,xmm0,0x2
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14];
VSHUFPS XMM2, XMM0, XMM1, 2;
VSHUFPS XMM0, XMM1, XMM2, 2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 5.99
- Reference cycles: 5.54
- UOPS_EXECUTED.THREAD: 6.0

VSHUFPS (XMM, XMM, XMM, I8) - Latency

Operands

Latency operand 2 → 1: 1

Latency operand 3 → 1: 1

Latency operand 2 → 1: 1

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 1

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)