VSQRTSD (XMM, XMM, XMM)

Experiment 1

Instruction: VSQRTSD XMM0, XMM2, XMM1
Chain instructions: VORPD XMM2, XMM0, XMM0; VORPD XMM2, XMM2, XMM1; VANDPD XMM2, XMM2, XMM1; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2;
Chain latency: ≥11

Code:

   0:	c5 eb 51 c1          	vsqrtsd xmm0,xmm2,xmm1
   4:	c5 f9 56 d0          	vorpd  xmm2,xmm0,xmm0
   8:	c5 e9 56 d1          	vorpd  xmm2,xmm2,xmm1
   c:	c5 e9 54 d1          	vandpd xmm2,xmm2,xmm1
  10:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  14:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  18:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  1c:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  20:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  24:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  28:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  2c:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x465a61fe1acdc21c;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 30.08
- Reference cycles: 27.01
- UOPS_EXECUTED.THREAD: 11.99

Experiment 2

Instruction: VSQRTSD XMM2, XMM2, XMM0

Code:

   0:	c5 eb 51 d0          	vsqrtsd xmm2,xmm2,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 13.0
- Reference cycles: 11.19
- UOPS_EXECUTED.THREAD: 1.01

Experiment 3

Instruction: VSQRTSD XMM0, XMM2, XMM1
Chain instructions: VORPD XMM2, XMM0, XMM0; VORPD XMM2, XMM2, XMM1; VANDPD XMM2, XMM2, XMM1; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2;
Chain latency: ≥11

Code:

   0:	c5 eb 51 c1          	vsqrtsd xmm0,xmm2,xmm1
   4:	c5 f9 56 d0          	vorpd  xmm2,xmm0,xmm0
   8:	c5 e9 56 d1          	vorpd  xmm2,xmm2,xmm1
   c:	c5 e9 54 d1          	vandpd xmm2,xmm2,xmm1
  10:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  14:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  18:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  1c:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  20:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  24:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  28:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  2c:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 25.11
- Reference cycles: 22.87
- UOPS_EXECUTED.THREAD: 11.99

Experiment 1

Instruction: VSQRTSD XMM0, XMM1, XMM2
Chain instructions: VORPD XMM2, XMM0, XMM0; VORPD XMM2, XMM2, XMM1; VANDPD XMM2, XMM2, XMM1; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2;
Chain latency: ≥11

Code:

   0:	c5 f3 51 c2          	vsqrtsd xmm0,xmm1,xmm2
   4:	c5 f9 56 d0          	vorpd  xmm2,xmm0,xmm0
   8:	c5 e9 56 d1          	vorpd  xmm2,xmm2,xmm1
   c:	c5 e9 54 d1          	vandpd xmm2,xmm2,xmm1
  10:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  14:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  18:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  1c:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  20:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  24:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  28:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  2c:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x465a61fe1acdc21c;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 30.01
- Reference cycles: 26.77
- UOPS_EXECUTED.THREAD: 12.01

Experiment 2

Instruction: VSQRTSD XMM2, XMM0, XMM2

Code:

   0:	c5 fb 51 d2          	vsqrtsd xmm2,xmm0,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 13.0
- Reference cycles: 11.92
- UOPS_EXECUTED.THREAD: 1.01

Experiment 3

Instruction: VSQRTSD XMM0, XMM1, XMM2
Chain instructions: VORPD XMM2, XMM0, XMM0; VORPD XMM2, XMM2, XMM1; VANDPD XMM2, XMM2, XMM1; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2; VORPD XMM2, XMM2, XMM2;
Chain latency: ≥11

Code:

   0:	c5 f3 51 c2          	vsqrtsd xmm0,xmm1,xmm2
   4:	c5 f9 56 d0          	vorpd  xmm2,xmm0,xmm0
   8:	c5 e9 56 d1          	vorpd  xmm2,xmm2,xmm1
   c:	c5 e9 54 d1          	vandpd xmm2,xmm2,xmm1
  10:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  14:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  18:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  1c:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  20:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  24:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  28:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2
  2c:	c5 e9 56 d2          	vorpd  xmm2,xmm2,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x3ff0000000000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 25.01
- Reference cycles: 23.12
- UOPS_EXECUTED.THREAD: 12.01

VSQRTSD (XMM, XMM, XMM) - Latency

Operands

Latency operand 2 → 1: ≤13

Latency operand 3 → 1: ≤13

Latency operand 2 → 1: ≤13

Experiment 1

Experiment 2

Experiment 3

Latency operand 3 → 1: ≤13

Experiment 1

Experiment 2

Experiment 3