IDIV (M32) - Latency


Operands


Latency operand 1 → 2 (address, base register): 15

Latency operand 1 → 2 (address, index register): 15

Latency operand 1 → 3 (address, base register): 19

Latency operand 1 → 3 (address, index register): 19

Latency operand 2 → 2: 11

Latency operand 2 → 3: 15

Latency operand 3 → 2: 15

Latency operand 3 → 3: 15


Latency operand 1 → 2 (address, base register): 15

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 2 (address, index register): 15

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, base register): 19

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, index register): 19

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 2: 11

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 3: 15

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 2: 15

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 3: 15

Experiment 1 (fast division)

Experiment 2 (slow division)