VFMADD213PS (YMM, YMM, M256)

Experiment 1

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.8
- UOPS_EXECUTED.THREAD: 2.0

Experiment 2

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.99
- Reference cycles: 6.57
- UOPS_EXECUTED.THREAD: 9.0

Experiment 3

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 7

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.64
- Reference cycles: 7.91
- UOPS_EXECUTED.THREAD: 9.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VFMADD213PS YMM0, YMM1, ymmword ptr [R14];
VFMADD213PS YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.43
- UOPS_EXECUTED.THREAD: 2.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VFMADD213PS YMM0, YMM1, ymmword ptr [R14];
VFMADD213PS YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.99
- Reference cycles: 6.57
- UOPS_EXECUTED.THREAD: 9.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 7

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VFMADD213PS YMM0, YMM1, ymmword ptr [R14];
VFMADD213PS YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.64
- Reference cycles: 7.3
- UOPS_EXECUTED.THREAD: 9.0

Latency operand 2 → 1: 4

Experiment 1

Instruction: VFMADD213PS YMM1, YMM0, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 c2 7d a8 0e       	vfmadd213ps ymm1,ymm0,YMMWORD PTR [r14]
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.99
- Reference cycles: 6.57
- UOPS_EXECUTED.THREAD: 9.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VFMADD213PS YMM1, YMM0, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;;VMOVUPD YMM1, YMM15
Chain latency: 7

Code:

   0:	c4 c2 7d a8 0e       	vfmadd213ps ymm1,ymm0,YMMWORD PTR [r14]
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  28:	c5 7d 11 f9          	vmovupd ymm1,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 6.57
- UOPS_EXECUTED.THREAD: 9.0

Experiment 3

Instruction: VFMADD213PS YMM1, YMM0, ymmword ptr [R14]
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 7

Code:

   0:	c4 c2 7d a8 0e       	vfmadd213ps ymm1,ymm0,YMMWORD PTR [r14]
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.64
- Reference cycles: 7.79
- UOPS_EXECUTED.THREAD: 9.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VFMADD213PS YMM1, YMM0, ymmword ptr [R14]
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;;VMOVUPD YMM1, YMM15
Chain latency: 7

Code:

   0:	c4 c2 7d a8 0e       	vfmadd213ps ymm1,ymm0,YMMWORD PTR [r14]
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  21:	c5 7d 11 f9          	vmovupd ymm1,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 12.6
- Reference cycles: 7.67
- UOPS_EXECUTED.THREAD: 9.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD213PS YMM1, YMM0, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 c2 7d a8 0e       	vfmadd213ps ymm1,ymm0,YMMWORD PTR [r14]
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14];
VFMADD213PS YMM1, YMM0, ymmword ptr [R14];
VFMADD213PS YMM0, YMM1, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.99
- Reference cycles: 6.57
- UOPS_EXECUTED.THREAD: 9.0

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VFMADD213PS YMM1, YMM0, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;;VMOVUPD YMM1, YMM15
Chain latency: 7

Code:

   0:	c4 c2 7d a8 0e       	vfmadd213ps ymm1,ymm0,YMMWORD PTR [r14]
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  28:	c5 7d 11 f9          	vmovupd ymm1,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14];
VFMADD213PS YMM1, YMM0, ymmword ptr [R14];
VFMADD213PS YMM0, YMM1, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 6.57
- UOPS_EXECUTED.THREAD: 9.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD213PS YMM1, YMM0, ymmword ptr [R14]
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 7

Code:

   0:	c4 c2 7d a8 0e       	vfmadd213ps ymm1,ymm0,YMMWORD PTR [r14]
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14];
VFMADD213PS YMM1, YMM0, ymmword ptr [R14];
VFMADD213PS YMM0, YMM1, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.64
- Reference cycles: 7.42
- UOPS_EXECUTED.THREAD: 9.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VFMADD213PS YMM1, YMM0, ymmword ptr [R14]
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;;VMOVUPD YMM1, YMM15
Chain latency: 7

Code:

   0:	c4 c2 7d a8 0e       	vfmadd213ps ymm1,ymm0,YMMWORD PTR [r14]
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  21:	c5 7d 11 f9          	vmovupd ymm1,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14];
VFMADD213PS YMM1, YMM0, ymmword ptr [R14];
VFMADD213PS YMM0, YMM1, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 12.6
- Reference cycles: 7.67
- UOPS_EXECUTED.THREAD: 9.0

Latency operand 3 → 1 (address, base register): ≤12

Experiment 1

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥7

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   a:	4d 31 e6             	xor    r14,r12
   d:	4d 31 e6             	xor    r14,r12
  10:	4d 31 e6             	xor    r14,r12
  13:	4d 31 e6             	xor    r14,r12
  16:	4d 31 e6             	xor    r14,r12
  19:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 19.0
- Reference cycles: 11.44
- UOPS_EXECUTED.THREAD: 9.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;;VMOVUPD YMM0, YMM15
Chain latency: ≥7

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   a:	4d 31 e6             	xor    r14,r12
   d:	4d 31 e6             	xor    r14,r12
  10:	4d 31 e6             	xor    r14,r12
  13:	4d 31 e6             	xor    r14,r12
  16:	4d 31 e6             	xor    r14,r12
  19:	4d 31 e6             	xor    r14,r12
  1c:	c5 7d 11 f8          	vmovupd ymm0,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 19.0
- Reference cycles: 11.44
- UOPS_EXECUTED.THREAD: 9.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥7

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   a:	4d 31 e6             	xor    r14,r12
   d:	4d 31 e6             	xor    r14,r12
  10:	4d 31 e6             	xor    r14,r12
  13:	4d 31 e6             	xor    r14,r12
  16:	4d 31 e6             	xor    r14,r12
  19:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VFMADD213PS YMM0, YMM1, ymmword ptr [R14];
VFMADD213PS YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 19.0
- Reference cycles: 11.56
- UOPS_EXECUTED.THREAD: 9.0

Experiment 4 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;;VMOVUPD YMM0, YMM15
Chain latency: ≥7

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   a:	4d 31 e6             	xor    r14,r12
   d:	4d 31 e6             	xor    r14,r12
  10:	4d 31 e6             	xor    r14,r12
  13:	4d 31 e6             	xor    r14,r12
  16:	4d 31 e6             	xor    r14,r12
  19:	4d 31 e6             	xor    r14,r12
  1c:	c5 7d 11 f8          	vmovupd ymm0,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VFMADD213PS YMM0, YMM1, ymmword ptr [R14];
VFMADD213PS YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 19.0
- Reference cycles: 11.44
- UOPS_EXECUTED.THREAD: 9.0

Latency operand 3 → 1 (address, index register): ≤12

Experiment 1

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14+R13]
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥7

Code:

   0:	c4 82 75 a8 04 2e    	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e5             	xor    r13,r12
   e:	4d 31 e5             	xor    r13,r12
  11:	4d 31 e5             	xor    r13,r12
  14:	4d 31 e5             	xor    r13,r12
  17:	4d 31 e5             	xor    r13,r12
  1a:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 19.0
- Reference cycles: 11.68
- UOPS_EXECUTED.THREAD: 9.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14+R13]
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;;VMOVUPD YMM0, YMM15
Chain latency: ≥7

Code:

   0:	c4 82 75 a8 04 2e    	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e5             	xor    r13,r12
   e:	4d 31 e5             	xor    r13,r12
  11:	4d 31 e5             	xor    r13,r12
  14:	4d 31 e5             	xor    r13,r12
  17:	4d 31 e5             	xor    r13,r12
  1a:	4d 31 e5             	xor    r13,r12
  1d:	c5 7d 11 f8          	vmovupd ymm0,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 19.0
- Reference cycles: 11.44
- UOPS_EXECUTED.THREAD: 9.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14+R13]
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥7

Code:

   0:	c4 82 75 a8 04 2e    	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e5             	xor    r13,r12
   e:	4d 31 e5             	xor    r13,r12
  11:	4d 31 e5             	xor    r13,r12
  14:	4d 31 e5             	xor    r13,r12
  17:	4d 31 e5             	xor    r13,r12
  1a:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
XOR R13, R13;
VFMADD213PS YMM0, YMM1, ymmword ptr [R14];
VFMADD213PS YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 19.0
- Reference cycles: 11.56
- UOPS_EXECUTED.THREAD: 9.0

Experiment 4 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14+R13]
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;;VMOVUPD YMM0, YMM15
Chain latency: ≥7

Code:

   0:	c4 82 75 a8 04 2e    	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e5             	xor    r13,r12
   e:	4d 31 e5             	xor    r13,r12
  11:	4d 31 e5             	xor    r13,r12
  14:	4d 31 e5             	xor    r13,r12
  17:	4d 31 e5             	xor    r13,r12
  1a:	4d 31 e5             	xor    r13,r12
  1d:	c5 7d 11 f8          	vmovupd ymm0,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
XOR R13, R13;
VFMADD213PS YMM0, YMM1, ymmword ptr [R14];
VFMADD213PS YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 19.0
- Reference cycles: 11.44
- UOPS_EXECUTED.THREAD: 9.0

Latency operand 3 → 1 (memory): ≤9

Experiment 1

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM13, YMM0, YMM0, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VMOVUPD [R14], YMM13
Chain latency: ≥8

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 7d c6 e8 00       	vshufpd ymm13,ymm0,ymm0,0x0
   a:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  10:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  16:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  1c:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  22:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  28:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  2e:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 17.0
- Reference cycles: 10.22
- UOPS_EXECUTED.THREAD: 11.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM13, YMM0, YMM0, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VMOVUPD [R14], YMM13;;VMOVUPD YMM0, YMM15
Chain latency: ≥8

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 7d c6 e8 00       	vshufpd ymm13,ymm0,ymm0,0x0
   a:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  10:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  16:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  1c:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  22:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  28:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  2e:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13
  33:	c5 7d 11 f8          	vmovupd ymm0,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 17.0
- Reference cycles: 10.22
- UOPS_EXECUTED.THREAD: 11.0

Experiment 3

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VPAND YMM13, YMM0, YMM0;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VMOVDQU [R14], YMM13
Chain latency: ≥8

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 7d db e8          	vpand  ymm13,ymm0,ymm0
   9:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
   e:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  13:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  18:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  1d:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  22:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  27:	c4 41 7e 7f 2e       	vmovdqu YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 17.66
- Reference cycles: 10.83
- UOPS_EXECUTED.THREAD: 11.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VPAND YMM13, YMM0, YMM0;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VMOVDQU [R14], YMM13;;VMOVUPD YMM0, YMM15
Chain latency: ≥8

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 7d db e8          	vpand  ymm13,ymm0,ymm0
   9:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
   e:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  13:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  18:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  1d:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  22:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  27:	c4 41 7e 7f 2e       	vmovdqu YMMWORD PTR [r14],ymm13
  2c:	c5 7d 11 f8          	vmovupd ymm0,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 17.55
- Reference cycles: 10.71
- UOPS_EXECUTED.THREAD: 11.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM13, YMM0, YMM0, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VMOVUPD [R14], YMM13
Chain latency: ≥8

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 7d c6 e8 00       	vshufpd ymm13,ymm0,ymm0,0x0
   a:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  10:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  16:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  1c:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  22:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  28:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  2e:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VFMADD213PS YMM0, YMM1, ymmword ptr [R14];
VFMADD213PS YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 17.0
- Reference cycles: 10.59
- UOPS_EXECUTED.THREAD: 11.0

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM13, YMM0, YMM0, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VMOVUPD [R14], YMM13;;VMOVUPD YMM0, YMM15
Chain latency: ≥8

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 7d c6 e8 00       	vshufpd ymm13,ymm0,ymm0,0x0
   a:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  10:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  16:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  1c:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  22:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  28:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  2e:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13
  33:	c5 7d 11 f8          	vmovupd ymm0,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VFMADD213PS YMM0, YMM1, ymmword ptr [R14];
VFMADD213PS YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 17.0
- Reference cycles: 10.46
- UOPS_EXECUTED.THREAD: 11.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VPAND YMM13, YMM0, YMM0;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VMOVDQU [R14], YMM13
Chain latency: ≥8

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 7d db e8          	vpand  ymm13,ymm0,ymm0
   9:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
   e:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  13:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  18:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  1d:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  22:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  27:	c4 41 7e 7f 2e       	vmovdqu YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VFMADD213PS YMM0, YMM1, ymmword ptr [R14];
VFMADD213PS YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 17.66
- Reference cycles: 10.34
- UOPS_EXECUTED.THREAD: 11.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VFMADD213PS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VPAND YMM13, YMM0, YMM0;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VMOVDQU [R14], YMM13;;VMOVUPD YMM0, YMM15
Chain latency: ≥8

Code:

   0:	c4 c2 75 a8 06       	vfmadd213ps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 7d db e8          	vpand  ymm13,ymm0,ymm0
   9:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
   e:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  13:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  18:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  1d:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  22:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  27:	c4 41 7e 7f 2e       	vmovdqu YMMWORD PTR [r14],ymm13
  2c:	c5 7d 11 f8          	vmovupd ymm0,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VFMADD213PS YMM0, YMM1, ymmword ptr [R14];
VFMADD213PS YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 17.55
- Reference cycles: 10.59
- UOPS_EXECUTED.THREAD: 11.0

VFMADD213PS (YMM, YMM, M256) - Latency

Operands

Latency operand 1 → 1: 4

Latency operand 2 → 1: 4

Latency operand 3 → 1 (address, base register): ≤12

Latency operand 3 → 1 (address, index register): ≤12

Latency operand 3 → 1 (memory): ≤9

Latency operand 1 → 1: 4

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: 4

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 3 → 1 (address, base register): ≤12

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 3 → 1 (address, index register): ≤12

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 3 → 1 (memory): ≤9

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)