VPERMT2W_Z (YMM, K, YMM, YMM)

Experiment 1

Instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2

Code:

   0:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 9.0
- Reference cycles: 5.72
- UOPS_EXECUTED.THREAD: 3.0

Experiment 2

Instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 13

Code:

   0:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2
   6:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  38:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  3d:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  42:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 21.99
- Reference cycles: 13.26
- UOPS_EXECUTED.THREAD: 16.0

Experiment 3

Instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 13

Code:

   0:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2
   6:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  32:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  36:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 22.0
- Reference cycles: 13.14
- UOPS_EXECUTED.THREAD: 16.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2

Code:

   0:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 9.0
- Reference cycles: 5.6
- UOPS_EXECUTED.THREAD: 3.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 13

Code:

   0:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2
   6:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  38:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  3d:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  42:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 21.99
- Reference cycles: 13.14
- UOPS_EXECUTED.THREAD: 16.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 13

Code:

   0:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2
   6:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  32:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  36:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 22.0
- Reference cycles: 13.14
- UOPS_EXECUTED.THREAD: 16.0

Latency operand 2 → 1: 5

Experiment 1

Instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2
Chain instruction: VPMOVQ2M K1, YMM0
Chain latency: 3

Code:

   0:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2
   6:	62 f2 fe 28 39 c8    	vpmovq2m k1,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 5.72
- UOPS_EXECUTED.THREAD: 4.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2
Chain instructions: VPMOVQ2M K1, YMM0;;VXORPS YMM0, YMM0, YMM0
Chain latency: 3

Code:

   0:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2
   6:	62 f2 fe 28 39 c8    	vpmovq2m k1,ymm0
   c:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 8.0
- Reference cycles: 4.87
- UOPS_EXECUTED.THREAD: 4.0

Experiment 3

Instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2
Chain instruction: VPTESTNMQ K1 {K1}, YMM0, YMM0
Chain latency: 3

Code:

   0:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2
   6:	62 f2 fe 29 27 c8    	vptestnmq k1{k1},ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 5.72
- UOPS_EXECUTED.THREAD: 4.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2
Chain instructions: VPTESTNMQ K1 {K1}, YMM0, YMM0;;VXORPS YMM0, YMM0, YMM0
Chain latency: 3

Code:

   0:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2
   6:	62 f2 fe 29 27 c8    	vptestnmq k1{k1},ymm0,ymm0
   c:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 8.0
- Reference cycles: 4.62
- UOPS_EXECUTED.THREAD: 4.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2
Chain instruction: VPMOVQ2M K1, YMM0
Chain latency: 3

Code:

   0:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2
   6:	62 f2 fe 28 39 c8    	vpmovq2m k1,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 5.72
- UOPS_EXECUTED.THREAD: 4.0

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2
Chain instructions: VPMOVQ2M K1, YMM0;;VXORPS YMM0, YMM0, YMM0
Chain latency: 3

Code:

   0:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2
   6:	62 f2 fe 28 39 c8    	vpmovq2m k1,ymm0
   c:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 8.0
- Reference cycles: 4.87
- UOPS_EXECUTED.THREAD: 4.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2
Chain instruction: VPTESTNMQ K1 {K1}, YMM0, YMM0
Chain latency: 3

Code:

   0:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2
   6:	62 f2 fe 29 27 c8    	vptestnmq k1{k1},ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 5.72
- UOPS_EXECUTED.THREAD: 4.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2
Chain instructions: VPTESTNMQ K1 {K1}, YMM0, YMM0;;VXORPS YMM0, YMM0, YMM0
Chain latency: 3

Code:

   0:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2
   6:	62 f2 fe 29 27 c8    	vptestnmq k1{k1},ymm0,ymm0
   c:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 8.0
- Reference cycles: 4.87
- UOPS_EXECUTED.THREAD: 4.0

Latency operand 3 → 1: 8

Experiment 1

Instruction: VPERMT2W YMM1 {K1}{z}, YMM0, YMM2
Chain instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2

Code:

   0:	62 f2 fd a9 7d ca    	vpermt2w ymm1{k1}{z},ymm0,ymm2
   6:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 16.0
- Reference cycles: 9.49
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM0, YMM2
Chain instructions: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2;VXORPS YMM1, YMM1, YMM1

Code:

   0:	62 f2 fd a9 7d ca    	vpermt2w ymm1{k1}{z},ymm0,ymm2
   6:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2
   c:	c5 f4 57 c9          	vxorps ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 16.0
- Reference cycles: 9.49
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3

Instruction: VPERMT2W YMM1 {K1}{z}, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 13

Code:

   0:	62 f2 fd a9 7d ca    	vpermt2w ymm1{k1}{z},ymm0,ymm2
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  38:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  3d:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  42:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 20.99
- Reference cycles: 12.41
- UOPS_EXECUTED.THREAD: 16.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;;VXORPS YMM1, YMM1, YMM1
Chain latency: 13

Code:

   0:	62 f2 fd a9 7d ca    	vpermt2w ymm1{k1}{z},ymm0,ymm2
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  38:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  3d:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  42:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  47:	c5 f4 57 c9          	vxorps ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 20.99
- Reference cycles: 12.53
- UOPS_EXECUTED.THREAD: 16.0

Experiment 5

Instruction: VPERMT2W YMM1 {K1}{z}, YMM0, YMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 13

Code:

   0:	62 f2 fd a9 7d ca    	vpermt2w ymm1{k1}{z},ymm0,ymm2
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  32:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  36:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 21.0
- Reference cycles: 12.41
- UOPS_EXECUTED.THREAD: 16.0

Experiment 6 (with dependency-breaking instructions)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM0, YMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;;VXORPS YMM1, YMM1, YMM1
Chain latency: 13

Code:

   0:	62 f2 fd a9 7d ca    	vpermt2w ymm1{k1}{z},ymm0,ymm2
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  32:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  36:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  3a:	c5 f4 57 c9          	vxorps ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 21.0
- Reference cycles: 12.65
- UOPS_EXECUTED.THREAD: 16.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM0, YMM2
Chain instruction: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2

Code:

   0:	62 f2 fd a9 7d ca    	vpermt2w ymm1{k1}{z},ymm0,ymm2
   6:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 16.0
- Reference cycles: 9.49
- UOPS_EXECUTED.THREAD: 6.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM0, YMM2
Chain instructions: VPERMT2W YMM0 {K1}{z}, YMM1, YMM2;VXORPS YMM1, YMM1, YMM1

Code:

   0:	62 f2 fd a9 7d ca    	vpermt2w ymm1{k1}{z},ymm0,ymm2
   6:	62 f2 f5 a9 7d c2    	vpermt2w ymm0{k1}{z},ymm1,ymm2
   c:	c5 f4 57 c9          	vxorps ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 16.0
- Reference cycles: 9.49
- UOPS_EXECUTED.THREAD: 6.0

Experiment 9 (source registers initialized by an instruction of the same kind)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 13

Code:

   0:	62 f2 fd a9 7d ca    	vpermt2w ymm1{k1}{z},ymm0,ymm2
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  38:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  3d:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  42:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 20.99
- Reference cycles: 12.65
- UOPS_EXECUTED.THREAD: 16.0

Experiment 10 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;;VXORPS YMM1, YMM1, YMM1
Chain latency: 13

Code:

   0:	62 f2 fd a9 7d ca    	vpermt2w ymm1{k1}{z},ymm0,ymm2
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  38:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  3d:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  42:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  47:	c5 f4 57 c9          	vxorps ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 20.99
- Reference cycles: 12.65
- UOPS_EXECUTED.THREAD: 16.0

Experiment 11 (source registers initialized by an instruction of the same kind)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM0, YMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 13

Code:

   0:	62 f2 fd a9 7d ca    	vpermt2w ymm1{k1}{z},ymm0,ymm2
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  32:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  36:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 21.0
- Reference cycles: 12.65
- UOPS_EXECUTED.THREAD: 16.0

Experiment 12 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM0, YMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;;VXORPS YMM1, YMM1, YMM1
Chain latency: 13

Code:

   0:	62 f2 fd a9 7d ca    	vpermt2w ymm1{k1}{z},ymm0,ymm2
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  32:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  36:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  3a:	c5 f4 57 c9          	vxorps ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 21.0
- Reference cycles: 12.41
- UOPS_EXECUTED.THREAD: 16.0

Latency operand 4 → 1: 8

Experiment 1

Instruction: VPERMT2W YMM1 {K1}{z}, YMM2, YMM0
Chain instruction: VPERMT2W YMM0 {K1}{z}, YMM2, YMM1

Code:

   0:	62 f2 ed a9 7d c8    	vpermt2w ymm1{k1}{z},ymm2,ymm0
   6:	62 f2 ed a9 7d c1    	vpermt2w ymm0{k1}{z},ymm2,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 16.0
- Reference cycles: 9.49
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM2, YMM0
Chain instructions: VPERMT2W YMM0 {K1}{z}, YMM2, YMM1;VXORPS YMM1, YMM1, YMM1

Code:

   0:	62 f2 ed a9 7d c8    	vpermt2w ymm1{k1}{z},ymm2,ymm0
   6:	62 f2 ed a9 7d c1    	vpermt2w ymm0{k1}{z},ymm2,ymm1
   c:	c5 f4 57 c9          	vxorps ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 16.0
- Reference cycles: 9.49
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3

Instruction: VPERMT2W YMM1 {K1}{z}, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 13

Code:

   0:	62 f2 ed a9 7d c8    	vpermt2w ymm1{k1}{z},ymm2,ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  38:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  3d:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  42:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 20.99
- Reference cycles: 12.53
- UOPS_EXECUTED.THREAD: 16.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;;VXORPS YMM1, YMM1, YMM1
Chain latency: 13

Code:

   0:	62 f2 ed a9 7d c8    	vpermt2w ymm1{k1}{z},ymm2,ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  38:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  3d:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  42:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  47:	c5 f4 57 c9          	vxorps ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 20.99
- Reference cycles: 12.41
- UOPS_EXECUTED.THREAD: 16.0

Experiment 5

Instruction: VPERMT2W YMM1 {K1}{z}, YMM2, YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 13

Code:

   0:	62 f2 ed a9 7d c8    	vpermt2w ymm1{k1}{z},ymm2,ymm0
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  32:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  36:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 21.0
- Reference cycles: 12.41
- UOPS_EXECUTED.THREAD: 16.0

Experiment 6 (with dependency-breaking instructions)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM2, YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;;VXORPS YMM1, YMM1, YMM1
Chain latency: 13

Code:

   0:	62 f2 ed a9 7d c8    	vpermt2w ymm1{k1}{z},ymm2,ymm0
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  32:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  36:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  3a:	c5 f4 57 c9          	vxorps ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 21.0
- Reference cycles: 12.41
- UOPS_EXECUTED.THREAD: 16.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM2, YMM0
Chain instruction: VPERMT2W YMM0 {K1}{z}, YMM2, YMM1

Code:

   0:	62 f2 ed a9 7d c8    	vpermt2w ymm1{k1}{z},ymm2,ymm0
   6:	62 f2 ed a9 7d c1    	vpermt2w ymm0{k1}{z},ymm2,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 16.0
- Reference cycles: 9.49
- UOPS_EXECUTED.THREAD: 6.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM2, YMM0
Chain instructions: VPERMT2W YMM0 {K1}{z}, YMM2, YMM1;VXORPS YMM1, YMM1, YMM1

Code:

   0:	62 f2 ed a9 7d c8    	vpermt2w ymm1{k1}{z},ymm2,ymm0
   6:	62 f2 ed a9 7d c1    	vpermt2w ymm0{k1}{z},ymm2,ymm1
   c:	c5 f4 57 c9          	vxorps ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 16.0
- Reference cycles: 9.49
- UOPS_EXECUTED.THREAD: 6.0

Experiment 9 (source registers initialized by an instruction of the same kind)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 13

Code:

   0:	62 f2 ed a9 7d c8    	vpermt2w ymm1{k1}{z},ymm2,ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  38:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  3d:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  42:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 20.99
- Reference cycles: 12.65
- UOPS_EXECUTED.THREAD: 16.0

Experiment 10 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;;VXORPS YMM1, YMM1, YMM1
Chain latency: 13

Code:

   0:	62 f2 ed a9 7d c8    	vpermt2w ymm1{k1}{z},ymm2,ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  38:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  3d:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  42:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  47:	c5 f4 57 c9          	vxorps ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 20.99
- Reference cycles: 12.41
- UOPS_EXECUTED.THREAD: 16.0

Experiment 11 (source registers initialized by an instruction of the same kind)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM2, YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 13

Code:

   0:	62 f2 ed a9 7d c8    	vpermt2w ymm1{k1}{z},ymm2,ymm0
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  32:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  36:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 21.0
- Reference cycles: 12.65
- UOPS_EXECUTED.THREAD: 16.0

Experiment 12 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPERMT2W YMM1 {K1}{z}, YMM2, YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;;VXORPS YMM1, YMM1, YMM1
Chain latency: 13

Code:

   0:	62 f2 ed a9 7d c8    	vpermt2w ymm1{k1}{z},ymm2,ymm0
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  32:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  36:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  3a:	c5 f4 57 c9          	vxorps ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0;
VPERMT2W YMM1  {K1}{z}, YMM0, YMM2;
VPERMT2W YMM2  {K1}{z}, YMM0, YMM1;
VPERMT2W YMM0  {K1}{z}, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 21.0
- Reference cycles: 12.53
- UOPS_EXECUTED.THREAD: 16.0

VPERMT2W_Z (YMM, K, YMM, YMM) - Latency

Operands

Latency operand 1 → 1: 9

Latency operand 2 → 1: 5

Latency operand 3 → 1: 8

Latency operand 4 → 1: 8

Latency operand 1 → 1: 9

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: 5

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 3 → 1: 8

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5

Experiment 6 (with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 9 (source registers initialized by an instruction of the same kind)

Experiment 10 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 11 (source registers initialized by an instruction of the same kind)

Experiment 12 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 4 → 1: 8

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5

Experiment 6 (with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 9 (source registers initialized by an instruction of the same kind)

Experiment 10 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 11 (source registers initialized by an instruction of the same kind)

Experiment 12 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)