MOVQ_0F7E (XMM, XMM) - Latency

Operands

Operand 1 (w): Register (XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15)
Operand 2 (r): Register (XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15)

Latency operand 2 → 1: 1

Latency operand 2 → 1: 1

Experiment 1

Instruction: {load} MOVQ XMM1, XMM0
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	f3 0f 7e c8          	movq   xmm1,xmm0
   4:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:
```
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 9.16
- UOPS_RETIRED.ANY: 6.0

Experiment 2

Instruction: {load} MOVQ XMM1, XMM0
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	f3 0f 7e c8          	movq   xmm1,xmm0
   4:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0

Init:
```
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 5.52
- UOPS_RETIRED.ANY: 6.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: {load} MOVQ XMM1, XMM0
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	f3 0f 7e c8          	movq   xmm1,xmm0
   4:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:
```
PXOR XMM0, XMM0;
{load} MOVQ XMM0, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 9.2
- UOPS_RETIRED.ANY: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: {load} MOVQ XMM1, XMM0
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	f3 0f 7e c8          	movq   xmm1,xmm0
   4:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0

Init:
```
PXOR XMM0, XMM0;
{load} MOVQ XMM0, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 5.48
- UOPS_RETIRED.ANY: 6.0