PCMPEQB (XMM, M128) - Latency


Operands


Latency operand 1 → 1: 2

Latency operand 2 → 1 (address, base register): ≤7

Latency operand 2 → 1 (address, index register): ≤7

Latency operand 2 → 1 (memory): ≤6


Latency operand 1 → 1: 2

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 1 (address, base register): ≤7

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 1 (address, index register): ≤7

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 1 (memory): ≤6

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)