VBLENDVPS (YMM, YMM, YMM, YMM)

Experiment 1

Instruction: VBLENDVPS YMM1, YMM0, YMM2, YMM3
Chain instructions: VANDPD YMM0, YMM1, YMM1;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 e3 7d 4a ca 30    	vblendvps ymm1,ymm0,ymm2,ymm3
   6:	c5 f5 54 c1          	vandpd ymm0,ymm1,ymm1
   a:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
   e:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  12:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  16:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14];
VXORPS YMM3, YMM3, YMM3

Show nanoBench command
Results:
- MPERF: 5.17
- APERF: 5.99
- UOPS: 6.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPS YMM1, YMM0, YMM2, YMM3
Chain instructions: VANDPD YMM0, YMM1, YMM1;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 e3 7d 4a ca 30    	vblendvps ymm1,ymm0,ymm2,ymm3
   6:	c5 f5 54 c1          	vandpd ymm0,ymm1,ymm1
   a:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
   e:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  12:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  16:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14];
VXORPS YMM3, YMM3, YMM3;
VBLENDVPS YMM0, YMM1, YMM2, YMM3;
VBLENDVPS YMM2, YMM0, YMM1, YMM3;
VBLENDVPS YMM3, YMM0, YMM1, YMM2

Show nanoBench command
Results:
- MPERF: 5.17
- APERF: 6.0
- UOPS: 6.0

Latency operand 3 → 1: 1

Experiment 1

Instruction: VBLENDVPS YMM1, YMM2, YMM0, YMM3
Chain instructions: VANDPD YMM0, YMM1, YMM1;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 e3 6d 4a c8 30    	vblendvps ymm1,ymm2,ymm0,ymm3
   6:	c5 f5 54 c1          	vandpd ymm0,ymm1,ymm1
   a:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
   e:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  12:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  16:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14];
VXORPS YMM3, YMM3, YMM3

Show nanoBench command
Results:
- MPERF: 5.17
- APERF: 6.0
- UOPS: 6.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPS YMM1, YMM2, YMM0, YMM3
Chain instructions: VANDPD YMM0, YMM1, YMM1;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 e3 6d 4a c8 30    	vblendvps ymm1,ymm2,ymm0,ymm3
   6:	c5 f5 54 c1          	vandpd ymm0,ymm1,ymm1
   a:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
   e:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  12:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  16:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14];
VXORPS YMM3, YMM3, YMM3;
VBLENDVPS YMM2, YMM0, YMM1, YMM3;
VBLENDVPS YMM0, YMM1, YMM2, YMM3;
VBLENDVPS YMM3, YMM0, YMM1, YMM2

Show nanoBench command
Results:
- MPERF: 5.17
- APERF: 6.0
- UOPS: 6.0

Latency operand 4 → 1: 1

Experiment 1

Instruction: VBLENDVPS YMM1, YMM2, YMM3, YMM0
Chain instructions: VANDPD YMM0, YMM1, YMM1;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 e3 6d 4a cb 00    	vblendvps ymm1,ymm2,ymm3,ymm0
   6:	c5 f5 54 c1          	vandpd ymm0,ymm1,ymm1
   a:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
   e:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  12:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  16:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- MPERF: 5.17
- APERF: 6.03
- UOPS: 6.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPS YMM1, YMM2, YMM3, YMM0
Chain instructions: VANDPD YMM0, YMM1, YMM1;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 e3 6d 4a cb 00    	vblendvps ymm1,ymm2,ymm3,ymm0
   6:	c5 f5 54 c1          	vandpd ymm0,ymm1,ymm1
   a:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
   e:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  12:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  16:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VMOVUPD YMM3, [R14];
VXORPS YMM0, YMM0, YMM0;
VBLENDVPS YMM2, YMM0, YMM1, YMM3;
VBLENDVPS YMM3, YMM0, YMM1, YMM2;
VBLENDVPS YMM0, YMM1, YMM2, YMM3

Show nanoBench command
Results:
- MPERF: 5.17
- APERF: 6.0
- UOPS: 6.0

VBLENDVPS (YMM, YMM, YMM, YMM) - Latency

Operands

Latency operand 2 → 1: 1

Latency operand 3 → 1: 1

Latency operand 4 → 1: 1

Latency operand 2 → 1: 1

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 1

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 4 → 1: 1

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)