VPCOMPRESSD (M512, K, ZMM)

Experiment 1

Instruction: VPCOMPRESSD zmmword ptr [R14] {K1}, ZMM0
Chain instructions: MOV R12, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12
Chain latency: ≥8

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	4d 8b 26             	mov    r12,QWORD PTR [r14]
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 31 e6             	xor    r14,r12
  1e:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- MPERF: 39.77
- APERF: 58.05
- UOPS: 17.0

Experiment 2 (with additional nop)

Instruction: VPCOMPRESSD zmmword ptr [R14] {K1}, ZMM0
Chain instructions: MOV R12, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥8

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	4d 8b 26             	mov    r12,QWORD PTR [r14]
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 31 e6             	xor    r14,r12
  1e:	4d 31 e6             	xor    r14,r12
  21:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- MPERF: 36.86
- APERF: 54.04
- UOPS: 18.0

Latency operand 1 → 1 (address, index register): ≤19

Experiment 1

Instruction: VPCOMPRESSD zmmword ptr [R14+R13] {K1}, ZMM0
Chain instructions: MOV R12, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12
Chain latency: ≥8

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	4f 8b 24 2e          	mov    r12,QWORD PTR [r14+r13*1]
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 31 e5             	xor    r13,r12
  20:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- MPERF: 18.56
- APERF: 27.1
- UOPS: 17.0

Experiment 2 (with additional nop)

Instruction: VPCOMPRESSD zmmword ptr [R14+R13] {K1}, ZMM0
Chain instructions: MOV R12, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12;nop
Chain latency: ≥8

Code:

   0:	62 92 7d 49 8b 04 2e 	vpcompressd ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	4f 8b 24 2e          	mov    r12,QWORD PTR [r14+r13*1]
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 31 e5             	xor    r13,r12
  20:	4d 31 e5             	xor    r13,r12
  23:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- MPERF: 18.56
- APERF: 27.11
- UOPS: 18.0

Latency operand 3 → 1: ≤18

Experiment 1

Instruction: VPCOMPRESSD zmmword ptr [R14] {K1}, ZMM0
Chain instructions: VMOVUPD XMM13, [R14];VANDPD XMM0, XMM13, XMM13;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0
Chain latency: ≥15

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	c4 41 79 10 2e       	vmovupd xmm13,XMMWORD PTR [r14]
   b:	c4 c1 11 54 c5       	vandpd xmm0,xmm13,xmm13
  10:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  14:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  18:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  1c:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  20:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  24:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- MPERF: 23.12
- APERF: 33.78
- UOPS: 16.0

Experiment 2

Instruction: VPCOMPRESSD zmmword ptr [R14] {K1}, ZMM0
Chain instructions: VMOVDQU XMM13, [R14];VPAND XMM0, XMM13, XMM13;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: ≥15

Code:

   0:	62 d2 7d 49 8b 06    	vpcompressd ZMMWORD PTR [r14]{k1},zmm0
   6:	c4 41 7a 6f 2e       	vmovdqu xmm13,XMMWORD PTR [r14]
   b:	c4 c1 11 db c5       	vpand  xmm0,xmm13,xmm13
  10:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  14:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  18:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1c:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  20:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  24:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- MPERF: 23.18
- APERF: 34.0
- UOPS: 16.0

VPCOMPRESSD (M512, K, ZMM) - Latency

Operands

Latency operand 1 → 1 (address, base register): ≤46

Latency operand 1 → 1 (address, index register): ≤19

Latency operand 3 → 1: ≤18

Latency operand 1 → 1 (address, base register): ≤46

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (address, index register): ≤19

Experiment 1

Experiment 2 (with additional nop)

Latency operand 3 → 1: ≤18

Experiment 1

Experiment 2