XCHG (R64, R64) - Port Usage

With blocking instructions for ports {'0', '1'}:

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	4d 87 c8             	xchg   r8,r9

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.22
- Reference cycles: 1.6
- UOPS_PORT_0: 4.97
- UOPS_PORT_1: 5.04

With blocking instructions for ports {'0', '5'}:

Code:

   0:	0f 6f c1             	movq   mm0,mm1
   3:	0f 6f d1             	movq   mm2,mm1
   6:	0f 6f d9             	movq   mm3,mm1
   9:	0f 6f e1             	movq   mm4,mm1
   c:	0f 6f e9             	movq   mm5,mm1
   f:	0f 6f f1             	movq   mm6,mm1
  12:	0f 6f f9             	movq   mm7,mm1
  15:	0f 6f c1             	movq   mm0,mm1
  18:	0f 6f d1             	movq   mm2,mm1
  1b:	0f 6f d9             	movq   mm3,mm1
  1e:	4d 87 c8             	xchg   r8,r9

Init:
```
PXOR MM1, MM1
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.11
- Reference cycles: 1.6
- UOPS_PORT_0: 4.99
- UOPS_PORT_5: 5.01

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c2 00       	rol    r10w,0x0
   5:	66 41 c1 c3 00       	rol    r11w,0x0
   a:	66 41 c1 c4 00       	rol    r12w,0x0
   f:	66 c1 c3 00          	rol    bx,0x0
  13:	66 c1 c1 00          	rol    cx,0x0
  17:	66 c1 c2 00          	rol    dx,0x0
  1b:	66 41 c1 c2 00       	rol    r10w,0x0
  20:	66 41 c1 c3 00       	rol    r11w,0x0
  25:	66 41 c1 c4 00       	rol    r12w,0x0
  2a:	66 c1 c3 00          	rol    bx,0x0
  2e:	4d 87 c8             	xchg   r8,r9

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.04
- Reference cycles: 1.6
- UOPS_PORT_0: 5.0
- UOPS_PORT_6: 4.98

With blocking instructions for ports {'1', '5'}:

Code:

   0:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
   4:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
   8:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
   c:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  10:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  14:	43 8d 14 6e          	lea    edx,[r14+r13*2]
  18:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  1c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  20:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  24:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  28:	4d 87 c8             	xchg   r8,r9

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.05
- Reference cycles: 1.55
- UOPS_PORT_1: 5.0
- UOPS_PORT_5: 5.03

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	4d 87 c8             	xchg   r8,r9

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 3.61
- Reference cycles: 1.14
- UOPS_PORT_0: 3.44
- UOPS_PORT_1: 3.46
- UOPS_PORT_5: 3.47

With blocking instructions for ports {'0', '1', '5', '6'}:

Code:

   0:	45 8d 56 08          	lea    r10d,[r14+0x8]
   4:	45 8d 5e 08          	lea    r11d,[r14+0x8]
   8:	45 8d 66 08          	lea    r12d,[r14+0x8]
   c:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  10:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  14:	41 8d 56 08          	lea    edx,[r14+0x8]
  18:	45 8d 56 08          	lea    r10d,[r14+0x8]
  1c:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  20:	45 8d 66 08          	lea    r12d,[r14+0x8]
  24:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  28:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  2c:	41 8d 56 08          	lea    edx,[r14+0x8]
  30:	4d 87 c8             	xchg   r8,r9

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 3.98
- Reference cycles: 1.24
- UOPS_PORT_0: 3.69
- UOPS_PORT_1: 3.7
- UOPS_PORT_6: 3.92
- UOPS_PORT_5: 3.7

⇨ 3 μops that can only use ports {'0', '1', '5', '6'}