MUL (R64) - Port Usage

With blocking instructions for port '0':

Code:

   0:	66 45 8d 0e          	lea    r9w,[r14]
   4:	66 45 8d 16          	lea    r10w,[r14]
   8:	66 45 8d 1e          	lea    r11w,[r14]
   c:	66 45 8d 26          	lea    r12w,[r14]
  10:	66 41 8d 1e          	lea    bx,[r14]
  14:	66 41 8d 0e          	lea    cx,[r14]
  18:	66 45 8d 0e          	lea    r9w,[r14]
  1c:	66 45 8d 16          	lea    r10w,[r14]
  20:	66 45 8d 1e          	lea    r11w,[r14]
  24:	66 45 8d 26          	lea    r12w,[r14]
  28:	66 41 8d 1e          	lea    bx,[r14]
  2c:	66 41 8d 0e          	lea    cx,[r14]
  30:	66 45 8d 0e          	lea    r9w,[r14]
  34:	66 45 8d 16          	lea    r10w,[r14]
  38:	49 f7 e0             	mul    r8

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 17.03
- Reference cycles: 17.11
- UOPS_PORT_0: 16.03

⇨ 2 μops that can only use port '0'

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	0f 55 c1             	andnps xmm0,xmm1
   3:	0f 55 d1             	andnps xmm2,xmm1
   6:	0f 55 d9             	andnps xmm3,xmm1
   9:	0f 55 e1             	andnps xmm4,xmm1
   c:	0f 55 e9             	andnps xmm5,xmm1
   f:	0f 55 f1             	andnps xmm6,xmm1
  12:	0f 55 f9             	andnps xmm7,xmm1
  15:	44 0f 55 c1          	andnps xmm8,xmm1
  19:	44 0f 55 c9          	andnps xmm9,xmm1
  1d:	44 0f 55 d1          	andnps xmm10,xmm1
  21:	44 0f 55 d9          	andnps xmm11,xmm1
  25:	44 0f 55 e1          	andnps xmm12,xmm1
  29:	0f 55 c1             	andnps xmm0,xmm1
  2c:	0f 55 d1             	andnps xmm2,xmm1
  2f:	0f 55 d9             	andnps xmm3,xmm1
  32:	0f 55 e1             	andnps xmm4,xmm1
  35:	0f 55 e9             	andnps xmm5,xmm1
  38:	0f 55 f1             	andnps xmm6,xmm1
  3b:	0f 55 f9             	andnps xmm7,xmm1
  3e:	44 0f 55 c1          	andnps xmm8,xmm1
  42:	44 0f 55 c9          	andnps xmm9,xmm1
  46:	44 0f 55 d1          	andnps xmm10,xmm1
  4a:	44 0f 55 d9          	andnps xmm11,xmm1
  4e:	44 0f 55 e1          	andnps xmm12,xmm1
  52:	0f 55 c1             	andnps xmm0,xmm1
  55:	0f 55 d1             	andnps xmm2,xmm1
  58:	0f 55 d9             	andnps xmm3,xmm1
  5b:	0f 55 e1             	andnps xmm4,xmm1
  5e:	0f 55 e9             	andnps xmm5,xmm1
  61:	0f 55 f1             	andnps xmm6,xmm1
  64:	0f 55 f9             	andnps xmm7,xmm1
  67:	44 0f 55 c1          	andnps xmm8,xmm1
  6b:	44 0f 55 c9          	andnps xmm9,xmm1
  6f:	44 0f 55 d1          	andnps xmm10,xmm1
  73:	44 0f 55 d9          	andnps xmm11,xmm1
  77:	44 0f 55 e1          	andnps xmm12,xmm1
  7b:	0f 55 c1             	andnps xmm0,xmm1
  7e:	0f 55 d1             	andnps xmm2,xmm1
  81:	0f 55 d9             	andnps xmm3,xmm1
  84:	0f 55 e1             	andnps xmm4,xmm1
  87:	0f 55 e9             	andnps xmm5,xmm1
  8a:	0f 55 f1             	andnps xmm6,xmm1
  8d:	49 f7 e0             	mul    r8

Init:

PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 43.0
- Core cycles: 43.52
- Reference cycles: 43.63
- UOPS_PORT_0: 7.74
- UOPS_PORT_1: 17.35
- UOPS_PORT_5: 19.91

⇨ One μop that can only use ports {'0', '1', '5'}