VPSRAD (YMM, YMM, I8)

With unroll_count=500 and no inner loop

Code:

   0:	c5 fd 72 e1 02       	vpsrad ymm0,ymm1,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.67
- Reference cycles: 0.74
- UOPS_RETIRED.ALL: 2.0
- UOPS_MS: 0.0

With loop_count=1000 and unroll_count=10

Code:

   0:	c5 fd 72 e1 02       	vpsrad ymm0,ymm1,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 0.67
- Reference cycles: 0.69
- UOPS_RETIRED.ALL: 2.2
- UOPS_MS: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c5 fd 72 e1 02       	vpsrad ymm0,ymm1,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 0.67
- Reference cycles: 0.69
- UOPS_RETIRED.ALL: 2.02
- UOPS_MS: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c5 fd 72 e1 02       	vpsrad ymm0,ymm1,0x2
   5:	c5 ed 72 e1 02       	vpsrad ymm2,ymm1,0x2
   a:	c5 e5 72 e1 02       	vpsrad ymm3,ymm1,0x2
   f:	c5 dd 72 e1 02       	vpsrad ymm4,ymm1,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.66
- Reference cycles: 2.88
- UOPS_RETIRED.ALL: 8.0
- UOPS_MS: 0.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c5 fd 72 e1 02       	vpsrad ymm0,ymm1,0x2
   5:	c5 ed 72 e1 02       	vpsrad ymm2,ymm1,0x2
   a:	c5 e5 72 e1 02       	vpsrad ymm3,ymm1,0x2
   f:	c5 dd 72 e1 02       	vpsrad ymm4,ymm1,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.68
- Reference cycles: 2.73
- UOPS_RETIRED.ALL: 9.0
- UOPS_MS: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c5 fd 72 e1 02       	vpsrad ymm0,ymm1,0x2
   5:	c5 ed 72 e1 02       	vpsrad ymm2,ymm1,0x2
   a:	c5 e5 72 e1 02       	vpsrad ymm3,ymm1,0x2
   f:	c5 dd 72 e1 02       	vpsrad ymm4,ymm1,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.68
- Reference cycles: 2.73
- UOPS_RETIRED.ALL: 8.1
- UOPS_MS: 0.0

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c5 fd 72 e1 02       	vpsrad ymm0,ymm1,0x2
   5:	c5 ed 72 e1 02       	vpsrad ymm2,ymm1,0x2
   a:	c5 e5 72 e1 02       	vpsrad ymm3,ymm1,0x2
   f:	c5 dd 72 e1 02       	vpsrad ymm4,ymm1,0x2
  14:	c5 d5 72 e1 02       	vpsrad ymm5,ymm1,0x2
  19:	c5 cd 72 e1 02       	vpsrad ymm6,ymm1,0x2
  1e:	c5 c5 72 e1 02       	vpsrad ymm7,ymm1,0x2
  23:	c5 bd 72 e1 02       	vpsrad ymm8,ymm1,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 5.32
- Reference cycles: 5.44
- UOPS_RETIRED.ALL: 16.0
- UOPS_MS: 0.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c5 fd 72 e1 02       	vpsrad ymm0,ymm1,0x2
   5:	c5 ed 72 e1 02       	vpsrad ymm2,ymm1,0x2
   a:	c5 e5 72 e1 02       	vpsrad ymm3,ymm1,0x2
   f:	c5 dd 72 e1 02       	vpsrad ymm4,ymm1,0x2
  14:	c5 d5 72 e1 02       	vpsrad ymm5,ymm1,0x2
  19:	c5 cd 72 e1 02       	vpsrad ymm6,ymm1,0x2
  1e:	c5 c5 72 e1 02       	vpsrad ymm7,ymm1,0x2
  23:	c5 bd 72 e1 02       	vpsrad ymm8,ymm1,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 5.35
- Reference cycles: 5.44
- UOPS_RETIRED.ALL: 18.0
- UOPS_MS: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c5 fd 72 e1 02       	vpsrad ymm0,ymm1,0x2
   5:	c5 ed 72 e1 02       	vpsrad ymm2,ymm1,0x2
   a:	c5 e5 72 e1 02       	vpsrad ymm3,ymm1,0x2
   f:	c5 dd 72 e1 02       	vpsrad ymm4,ymm1,0x2
  14:	c5 d5 72 e1 02       	vpsrad ymm5,ymm1,0x2
  19:	c5 cd 72 e1 02       	vpsrad ymm6,ymm1,0x2
  1e:	c5 c5 72 e1 02       	vpsrad ymm7,ymm1,0x2
  23:	c5 bd 72 e1 02       	vpsrad ymm8,ymm1,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 5.35
- Reference cycles: 5.49
- UOPS_RETIRED.ALL: 16.2
- UOPS_MS: 0.0

With 12 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c5 fd 72 e1 02       	vpsrad ymm0,ymm1,0x2
   5:	c5 ed 72 e1 02       	vpsrad ymm2,ymm1,0x2
   a:	c5 e5 72 e1 02       	vpsrad ymm3,ymm1,0x2
   f:	c5 dd 72 e1 02       	vpsrad ymm4,ymm1,0x2
  14:	c5 d5 72 e1 02       	vpsrad ymm5,ymm1,0x2
  19:	c5 cd 72 e1 02       	vpsrad ymm6,ymm1,0x2
  1e:	c5 c5 72 e1 02       	vpsrad ymm7,ymm1,0x2
  23:	c5 bd 72 e1 02       	vpsrad ymm8,ymm1,0x2
  28:	c5 b5 72 e1 02       	vpsrad ymm9,ymm1,0x2
  2d:	c5 ad 72 e1 02       	vpsrad ymm10,ymm1,0x2
  32:	c5 a5 72 e1 02       	vpsrad ymm11,ymm1,0x2
  37:	c5 9d 72 e1 02       	vpsrad ymm12,ymm1,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 8.02
- Reference cycles: 7.68
- UOPS_RETIRED.ALL: 24.0
- UOPS_MS: 0.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c5 fd 72 e1 02       	vpsrad ymm0,ymm1,0x2
   5:	c5 ed 72 e1 02       	vpsrad ymm2,ymm1,0x2
   a:	c5 e5 72 e1 02       	vpsrad ymm3,ymm1,0x2
   f:	c5 dd 72 e1 02       	vpsrad ymm4,ymm1,0x2
  14:	c5 d5 72 e1 02       	vpsrad ymm5,ymm1,0x2
  19:	c5 cd 72 e1 02       	vpsrad ymm6,ymm1,0x2
  1e:	c5 c5 72 e1 02       	vpsrad ymm7,ymm1,0x2
  23:	c5 bd 72 e1 02       	vpsrad ymm8,ymm1,0x2
  28:	c5 b5 72 e1 02       	vpsrad ymm9,ymm1,0x2
  2d:	c5 ad 72 e1 02       	vpsrad ymm10,ymm1,0x2
  32:	c5 a5 72 e1 02       	vpsrad ymm11,ymm1,0x2
  37:	c5 9d 72 e1 02       	vpsrad ymm12,ymm1,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 8.02
- Reference cycles: 8.16
- UOPS_RETIRED.ALL: 26.0
- UOPS_MS: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c5 fd 72 e1 02       	vpsrad ymm0,ymm1,0x2
   5:	c5 ed 72 e1 02       	vpsrad ymm2,ymm1,0x2
   a:	c5 e5 72 e1 02       	vpsrad ymm3,ymm1,0x2
   f:	c5 dd 72 e1 02       	vpsrad ymm4,ymm1,0x2
  14:	c5 d5 72 e1 02       	vpsrad ymm5,ymm1,0x2
  19:	c5 cd 72 e1 02       	vpsrad ymm6,ymm1,0x2
  1e:	c5 c5 72 e1 02       	vpsrad ymm7,ymm1,0x2
  23:	c5 bd 72 e1 02       	vpsrad ymm8,ymm1,0x2
  28:	c5 b5 72 e1 02       	vpsrad ymm9,ymm1,0x2
  2d:	c5 ad 72 e1 02       	vpsrad ymm10,ymm1,0x2
  32:	c5 a5 72 e1 02       	vpsrad ymm11,ymm1,0x2
  37:	c5 9d 72 e1 02       	vpsrad ymm12,ymm1,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 12.2
- Core cycles: 8.02
- Reference cycles: 8.22
- UOPS_RETIRED.ALL: 24.2
- UOPS_MS: 0.0

With the same register for for different operands

With unroll_count=500 and no inner loop

Code:

   0:	c5 fd 72 e0 02       	vpsrad ymm0,ymm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.2
- Reference cycles: 1.22
- UOPS_RETIRED.ALL: 2.0
- UOPS_MS: 0.0

With loop_count=1000 and unroll_count=10

Code:

   0:	c5 fd 72 e0 02       	vpsrad ymm0,ymm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.23
- Reference cycles: 1.26
- UOPS_RETIRED.ALL: 2.2
- UOPS_MS: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c5 fd 72 e0 02       	vpsrad ymm0,ymm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.17
- Reference cycles: 1.2
- UOPS_RETIRED.ALL: 2.02
- UOPS_MS: 0.0

VPSRAD (YMM, YMM, I8) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 12 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100