VPERMILPS_EVEX (XMM, M32

With unroll_count=500 and no inner loop

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.77
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 0.77
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 0.7
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.0
- Reference cycles: 0.77
- UOPS_EXECUTED.THREAD: 1.99
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.0
- Reference cycles: 0.77
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 5 NOPs

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop
   b:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 2.0
- Reference cycles: 1.54
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 7.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.76
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2
   7:	62 d3 7d 18 04 4e 01 	vpermilps xmm1,DWORD PTR [r14+0x4]{1to4},0x2
   e:	02 
   f:	62 d3 7d 18 04 56 02 	vpermilps xmm2,DWORD PTR [r14+0x8]{1to4},0x2
  16:	02 
  17:	62 d3 7d 18 04 5e 03 	vpermilps xmm3,DWORD PTR [r14+0xc]{1to4},0x2
  1e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.12
- UOPS_EXECUTED.THREAD: 8.01
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2
   7:	62 d3 7d 18 04 4e 01 	vpermilps xmm1,DWORD PTR [r14+0x4]{1to4},0x2
   e:	02 
   f:	62 d3 7d 18 04 56 02 	vpermilps xmm2,DWORD PTR [r14+0x8]{1to4},0x2
  16:	02 
  17:	62 d3 7d 18 04 5e 03 	vpermilps xmm3,DWORD PTR [r14+0xc]{1to4},0x2
  1e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 3.02
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.03
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2
   7:	62 d3 7d 18 04 4e 01 	vpermilps xmm1,DWORD PTR [r14+0x4]{1to4},0x2
   e:	02 
   f:	62 d3 7d 18 04 56 02 	vpermilps xmm2,DWORD PTR [r14+0x8]{1to4},0x2
  16:	02 
  17:	62 d3 7d 18 04 5e 03 	vpermilps xmm3,DWORD PTR [r14+0xc]{1to4},0x2
  1e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.0
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.07
- UOPS_MS: 0.03
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2
   7:	62 d3 7d 18 04 4e 01 	vpermilps xmm1,DWORD PTR [r14+0x4]{1to4},0x2
   e:	02 
   f:	62 d3 7d 18 04 56 02 	vpermilps xmm2,DWORD PTR [r14+0x8]{1to4},0x2
  16:	02 
  17:	62 d3 7d 18 04 5e 03 	vpermilps xmm3,DWORD PTR [r14+0xc]{1to4},0x2
  1e:	02 
  1f:	62 d3 7d 18 04 66 04 	vpermilps xmm4,DWORD PTR [r14+0x10]{1to4},0x2
  26:	02 
  27:	62 d3 7d 18 04 6e 05 	vpermilps xmm5,DWORD PTR [r14+0x14]{1to4},0x2
  2e:	02 
  2f:	62 d3 7d 18 04 76 06 	vpermilps xmm6,DWORD PTR [r14+0x18]{1to4},0x2
  36:	02 
  37:	62 d3 7d 18 04 7e 07 	vpermilps xmm7,DWORD PTR [r14+0x1c]{1to4},0x2
  3e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 6.08
- UOPS_EXECUTED.THREAD: 16.02
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 8.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2
   7:	62 d3 7d 18 04 4e 01 	vpermilps xmm1,DWORD PTR [r14+0x4]{1to4},0x2
   e:	02 
   f:	62 d3 7d 18 04 56 02 	vpermilps xmm2,DWORD PTR [r14+0x8]{1to4},0x2
  16:	02 
  17:	62 d3 7d 18 04 5e 03 	vpermilps xmm3,DWORD PTR [r14+0xc]{1to4},0x2
  1e:	02 
  1f:	62 d3 7d 18 04 66 04 	vpermilps xmm4,DWORD PTR [r14+0x10]{1to4},0x2
  26:	02 
  27:	62 d3 7d 18 04 6e 05 	vpermilps xmm5,DWORD PTR [r14+0x14]{1to4},0x2
  2e:	02 
  2f:	62 d3 7d 18 04 76 06 	vpermilps xmm6,DWORD PTR [r14+0x18]{1to4},0x2
  36:	02 
  37:	62 d3 7d 18 04 7e 07 	vpermilps xmm7,DWORD PTR [r14+0x1c]{1to4},0x2
  3e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 6.02
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.0
- UOPS_MS: 0.05
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 8.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2
   7:	62 d3 7d 18 04 4e 01 	vpermilps xmm1,DWORD PTR [r14+0x4]{1to4},0x2
   e:	02 
   f:	62 d3 7d 18 04 56 02 	vpermilps xmm2,DWORD PTR [r14+0x8]{1to4},0x2
  16:	02 
  17:	62 d3 7d 18 04 5e 03 	vpermilps xmm3,DWORD PTR [r14+0xc]{1to4},0x2
  1e:	02 
  1f:	62 d3 7d 18 04 66 04 	vpermilps xmm4,DWORD PTR [r14+0x10]{1to4},0x2
  26:	02 
  27:	62 d3 7d 18 04 6e 05 	vpermilps xmm5,DWORD PTR [r14+0x14]{1to4},0x2
  2e:	02 
  2f:	62 d3 7d 18 04 76 06 	vpermilps xmm6,DWORD PTR [r14+0x18]{1to4},0x2
  36:	02 
  37:	62 d3 7d 18 04 7e 07 	vpermilps xmm7,DWORD PTR [r14+0x1c]{1to4},0x2
  3e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 6.02
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.13
- UOPS_MS: 0.05
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 8.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2
   7:	62 d3 7d 18 04 4e 01 	vpermilps xmm1,DWORD PTR [r14+0x4]{1to4},0x2
   e:	02 
   f:	62 d3 7d 18 04 56 02 	vpermilps xmm2,DWORD PTR [r14+0x8]{1to4},0x2
  16:	02 
  17:	62 d3 7d 18 04 5e 03 	vpermilps xmm3,DWORD PTR [r14+0xc]{1to4},0x2
  1e:	02 
  1f:	62 d3 7d 18 04 66 04 	vpermilps xmm4,DWORD PTR [r14+0x10]{1to4},0x2
  26:	02 
  27:	62 d3 7d 18 04 6e 05 	vpermilps xmm5,DWORD PTR [r14+0x14]{1to4},0x2
  2e:	02 
  2f:	62 d3 7d 18 04 76 06 	vpermilps xmm6,DWORD PTR [r14+0x18]{1to4},0x2
  36:	02 
  37:	62 d3 7d 18 04 7e 07 	vpermilps xmm7,DWORD PTR [r14+0x1c]{1to4},0x2
  3e:	02 
  3f:	62 53 7d 18 04 46 08 	vpermilps xmm8,DWORD PTR [r14+0x20]{1to4},0x2
  46:	02 
  47:	62 53 7d 18 04 4e 09 	vpermilps xmm9,DWORD PTR [r14+0x24]{1to4},0x2
  4e:	02 
  4f:	62 53 7d 18 04 56 0a 	vpermilps xmm10,DWORD PTR [r14+0x28]{1to4},0x2
  56:	02 
  57:	62 53 7d 18 04 5e 0b 	vpermilps xmm11,DWORD PTR [r14+0x2c]{1to4},0x2
  5e:	02 
  5f:	62 53 7d 18 04 66 0c 	vpermilps xmm12,DWORD PTR [r14+0x30]{1to4},0x2
  66:	02 
  67:	62 c3 7d 18 04 46 0d 	vpermilps xmm16,DWORD PTR [r14+0x34]{1to4},0x2
  6e:	02 
  6f:	62 c3 7d 18 04 4e 0e 	vpermilps xmm17,DWORD PTR [r14+0x38]{1to4},0x2
  76:	02 
  77:	62 c3 7d 18 04 56 0f 	vpermilps xmm18,DWORD PTR [r14+0x3c]{1to4},0x2
  7e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX;
MOV [R14+32], RAX;
MOV [R14+36], RAX;
MOV [R14+40], RAX;
MOV [R14+44], RAX;
MOV [R14+48], RAX;
MOV [R14+52], RAX;
MOV [R14+56], RAX;
MOV [R14+60], RAX

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 12.0
- UOPS_EXECUTED.THREAD: 32.04
- RETIRE_SLOTS: 32.01
- UOPS_MITE: 32.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 16.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2
   7:	62 d3 7d 18 04 4e 01 	vpermilps xmm1,DWORD PTR [r14+0x4]{1to4},0x2
   e:	02 
   f:	62 d3 7d 18 04 56 02 	vpermilps xmm2,DWORD PTR [r14+0x8]{1to4},0x2
  16:	02 
  17:	62 d3 7d 18 04 5e 03 	vpermilps xmm3,DWORD PTR [r14+0xc]{1to4},0x2
  1e:	02 
  1f:	62 d3 7d 18 04 66 04 	vpermilps xmm4,DWORD PTR [r14+0x10]{1to4},0x2
  26:	02 
  27:	62 d3 7d 18 04 6e 05 	vpermilps xmm5,DWORD PTR [r14+0x14]{1to4},0x2
  2e:	02 
  2f:	62 d3 7d 18 04 76 06 	vpermilps xmm6,DWORD PTR [r14+0x18]{1to4},0x2
  36:	02 
  37:	62 d3 7d 18 04 7e 07 	vpermilps xmm7,DWORD PTR [r14+0x1c]{1to4},0x2
  3e:	02 
  3f:	62 53 7d 18 04 46 08 	vpermilps xmm8,DWORD PTR [r14+0x20]{1to4},0x2
  46:	02 
  47:	62 53 7d 18 04 4e 09 	vpermilps xmm9,DWORD PTR [r14+0x24]{1to4},0x2
  4e:	02 
  4f:	62 53 7d 18 04 56 0a 	vpermilps xmm10,DWORD PTR [r14+0x28]{1to4},0x2
  56:	02 
  57:	62 53 7d 18 04 5e 0b 	vpermilps xmm11,DWORD PTR [r14+0x2c]{1to4},0x2
  5e:	02 
  5f:	62 53 7d 18 04 66 0c 	vpermilps xmm12,DWORD PTR [r14+0x30]{1to4},0x2
  66:	02 
  67:	62 c3 7d 18 04 46 0d 	vpermilps xmm16,DWORD PTR [r14+0x34]{1to4},0x2
  6e:	02 
  6f:	62 c3 7d 18 04 4e 0e 	vpermilps xmm17,DWORD PTR [r14+0x38]{1to4},0x2
  76:	02 
  77:	62 c3 7d 18 04 56 0f 	vpermilps xmm18,DWORD PTR [r14+0x3c]{1to4},0x2
  7e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX;
MOV [R14+32], RAX;
MOV [R14+36], RAX;
MOV [R14+40], RAX;
MOV [R14+44], RAX;
MOV [R14+48], RAX;
MOV [R14+52], RAX;
MOV [R14+56], RAX;
MOV [R14+60], RAX

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.01
- Reference cycles: 12.02
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.0
- UOPS_MS: 0.04
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 16.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 d3 7d 18 04 06 02 	vpermilps xmm0,DWORD PTR [r14]{1to4},0x2
   7:	62 d3 7d 18 04 4e 01 	vpermilps xmm1,DWORD PTR [r14+0x4]{1to4},0x2
   e:	02 
   f:	62 d3 7d 18 04 56 02 	vpermilps xmm2,DWORD PTR [r14+0x8]{1to4},0x2
  16:	02 
  17:	62 d3 7d 18 04 5e 03 	vpermilps xmm3,DWORD PTR [r14+0xc]{1to4},0x2
  1e:	02 
  1f:	62 d3 7d 18 04 66 04 	vpermilps xmm4,DWORD PTR [r14+0x10]{1to4},0x2
  26:	02 
  27:	62 d3 7d 18 04 6e 05 	vpermilps xmm5,DWORD PTR [r14+0x14]{1to4},0x2
  2e:	02 
  2f:	62 d3 7d 18 04 76 06 	vpermilps xmm6,DWORD PTR [r14+0x18]{1to4},0x2
  36:	02 
  37:	62 d3 7d 18 04 7e 07 	vpermilps xmm7,DWORD PTR [r14+0x1c]{1to4},0x2
  3e:	02 
  3f:	62 53 7d 18 04 46 08 	vpermilps xmm8,DWORD PTR [r14+0x20]{1to4},0x2
  46:	02 
  47:	62 53 7d 18 04 4e 09 	vpermilps xmm9,DWORD PTR [r14+0x24]{1to4},0x2
  4e:	02 
  4f:	62 53 7d 18 04 56 0a 	vpermilps xmm10,DWORD PTR [r14+0x28]{1to4},0x2
  56:	02 
  57:	62 53 7d 18 04 5e 0b 	vpermilps xmm11,DWORD PTR [r14+0x2c]{1to4},0x2
  5e:	02 
  5f:	62 53 7d 18 04 66 0c 	vpermilps xmm12,DWORD PTR [r14+0x30]{1to4},0x2
  66:	02 
  67:	62 c3 7d 18 04 46 0d 	vpermilps xmm16,DWORD PTR [r14+0x34]{1to4},0x2
  6e:	02 
  6f:	62 c3 7d 18 04 4e 0e 	vpermilps xmm17,DWORD PTR [r14+0x38]{1to4},0x2
  76:	02 
  77:	62 c3 7d 18 04 56 0f 	vpermilps xmm18,DWORD PTR [r14+0x3c]{1to4},0x2
  7e:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX;
MOV [R14+32], RAX;
MOV [R14+36], RAX;
MOV [R14+40], RAX;
MOV [R14+44], RAX;
MOV [R14+48], RAX;
MOV [R14+52], RAX;
MOV [R14+56], RAX;
MOV [R14+60], RAX

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.01
- Reference cycles: 12.02
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.29
- UOPS_MS: 0.03
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 16.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.15

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.77
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02 
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 0.74
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02 
   8:	90                   	nop
   9:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 1.0
- Reference cycles: 0.83
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02 
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.0
- Reference cycles: 0.74
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02 
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop
   b:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.0
- Reference cycles: 0.74
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 5 NOPs

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02 
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop
   b:	90                   	nop
   c:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 2.0
- Reference cycles: 1.54
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 7.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.01
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02 
   8:	62 93 7d 18 04 4c 2e 	vpermilps xmm1,DWORD PTR [r14+r13*1+0x4]{1to4},0x2
   f:	01 02 
  11:	62 93 7d 18 04 54 2e 	vpermilps xmm2,DWORD PTR [r14+r13*1+0x8]{1to4},0x2
  18:	02 02 
  1a:	62 93 7d 18 04 5c 2e 	vpermilps xmm3,DWORD PTR [r14+r13*1+0xc]{1to4},0x2
  21:	03 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.12
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02 
   8:	62 93 7d 18 04 4c 2e 	vpermilps xmm1,DWORD PTR [r14+r13*1+0x4]{1to4},0x2
   f:	01 02 
  11:	62 93 7d 18 04 54 2e 	vpermilps xmm2,DWORD PTR [r14+r13*1+0x8]{1to4},0x2
  18:	02 02 
  1a:	62 93 7d 18 04 5c 2e 	vpermilps xmm3,DWORD PTR [r14+r13*1+0xc]{1to4},0x2
  21:	03 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.03
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02 
   8:	62 93 7d 18 04 4c 2e 	vpermilps xmm1,DWORD PTR [r14+r13*1+0x4]{1to4},0x2
   f:	01 02 
  11:	62 93 7d 18 04 54 2e 	vpermilps xmm2,DWORD PTR [r14+r13*1+0x8]{1to4},0x2
  18:	02 02 
  1a:	62 93 7d 18 04 5c 2e 	vpermilps xmm3,DWORD PTR [r14+r13*1+0xc]{1to4},0x2
  21:	03 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.0
- Reference cycles: 2.99
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.07
- UOPS_MS: 0.03
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02 
   8:	62 93 7d 18 04 4c 2e 	vpermilps xmm1,DWORD PTR [r14+r13*1+0x4]{1to4},0x2
   f:	01 02 
  11:	62 93 7d 18 04 54 2e 	vpermilps xmm2,DWORD PTR [r14+r13*1+0x8]{1to4},0x2
  18:	02 02 
  1a:	62 93 7d 18 04 5c 2e 	vpermilps xmm3,DWORD PTR [r14+r13*1+0xc]{1to4},0x2
  21:	03 02 
  23:	62 93 7d 18 04 64 2e 	vpermilps xmm4,DWORD PTR [r14+r13*1+0x10]{1to4},0x2
  2a:	04 02 
  2c:	62 93 7d 18 04 6c 2e 	vpermilps xmm5,DWORD PTR [r14+r13*1+0x14]{1to4},0x2
  33:	05 02 
  35:	62 93 7d 18 04 74 2e 	vpermilps xmm6,DWORD PTR [r14+r13*1+0x18]{1to4},0x2
  3c:	06 02 
  3e:	62 93 7d 18 04 7c 2e 	vpermilps xmm7,DWORD PTR [r14+r13*1+0x1c]{1to4},0x2
  45:	07 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 6.08
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 8.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02 
   8:	62 93 7d 18 04 4c 2e 	vpermilps xmm1,DWORD PTR [r14+r13*1+0x4]{1to4},0x2
   f:	01 02 
  11:	62 93 7d 18 04 54 2e 	vpermilps xmm2,DWORD PTR [r14+r13*1+0x8]{1to4},0x2
  18:	02 02 
  1a:	62 93 7d 18 04 5c 2e 	vpermilps xmm3,DWORD PTR [r14+r13*1+0xc]{1to4},0x2
  21:	03 02 
  23:	62 93 7d 18 04 64 2e 	vpermilps xmm4,DWORD PTR [r14+r13*1+0x10]{1to4},0x2
  2a:	04 02 
  2c:	62 93 7d 18 04 6c 2e 	vpermilps xmm5,DWORD PTR [r14+r13*1+0x14]{1to4},0x2
  33:	05 02 
  35:	62 93 7d 18 04 74 2e 	vpermilps xmm6,DWORD PTR [r14+r13*1+0x18]{1to4},0x2
  3c:	06 02 
  3e:	62 93 7d 18 04 7c 2e 	vpermilps xmm7,DWORD PTR [r14+r13*1+0x1c]{1to4},0x2
  45:	07 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 6.02
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: -0.01
- UOPS_MS: 0.06
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 8.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02 
   8:	62 93 7d 18 04 4c 2e 	vpermilps xmm1,DWORD PTR [r14+r13*1+0x4]{1to4},0x2
   f:	01 02 
  11:	62 93 7d 18 04 54 2e 	vpermilps xmm2,DWORD PTR [r14+r13*1+0x8]{1to4},0x2
  18:	02 02 
  1a:	62 93 7d 18 04 5c 2e 	vpermilps xmm3,DWORD PTR [r14+r13*1+0xc]{1to4},0x2
  21:	03 02 
  23:	62 93 7d 18 04 64 2e 	vpermilps xmm4,DWORD PTR [r14+r13*1+0x10]{1to4},0x2
  2a:	04 02 
  2c:	62 93 7d 18 04 6c 2e 	vpermilps xmm5,DWORD PTR [r14+r13*1+0x14]{1to4},0x2
  33:	05 02 
  35:	62 93 7d 18 04 74 2e 	vpermilps xmm6,DWORD PTR [r14+r13*1+0x18]{1to4},0x2
  3c:	06 02 
  3e:	62 93 7d 18 04 7c 2e 	vpermilps xmm7,DWORD PTR [r14+r13*1+0x1c]{1to4},0x2
  45:	07 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 6.05
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.14
- UOPS_MS: 0.06
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 8.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02 
   8:	62 93 7d 18 04 4c 2e 	vpermilps xmm1,DWORD PTR [r14+r13*1+0x4]{1to4},0x2
   f:	01 02 
  11:	62 93 7d 18 04 54 2e 	vpermilps xmm2,DWORD PTR [r14+r13*1+0x8]{1to4},0x2
  18:	02 02 
  1a:	62 93 7d 18 04 5c 2e 	vpermilps xmm3,DWORD PTR [r14+r13*1+0xc]{1to4},0x2
  21:	03 02 
  23:	62 93 7d 18 04 64 2e 	vpermilps xmm4,DWORD PTR [r14+r13*1+0x10]{1to4},0x2
  2a:	04 02 
  2c:	62 93 7d 18 04 6c 2e 	vpermilps xmm5,DWORD PTR [r14+r13*1+0x14]{1to4},0x2
  33:	05 02 
  35:	62 93 7d 18 04 74 2e 	vpermilps xmm6,DWORD PTR [r14+r13*1+0x18]{1to4},0x2
  3c:	06 02 
  3e:	62 93 7d 18 04 7c 2e 	vpermilps xmm7,DWORD PTR [r14+r13*1+0x1c]{1to4},0x2
  45:	07 02 
  47:	62 13 7d 18 04 44 2e 	vpermilps xmm8,DWORD PTR [r14+r13*1+0x20]{1to4},0x2
  4e:	08 02 
  50:	62 13 7d 18 04 4c 2e 	vpermilps xmm9,DWORD PTR [r14+r13*1+0x24]{1to4},0x2
  57:	09 02 
  59:	62 13 7d 18 04 54 2e 	vpermilps xmm10,DWORD PTR [r14+r13*1+0x28]{1to4},0x2
  60:	0a 02 
  62:	62 13 7d 18 04 5c 2e 	vpermilps xmm11,DWORD PTR [r14+r13*1+0x2c]{1to4},0x2
  69:	0b 02 
  6b:	62 13 7d 18 04 64 2e 	vpermilps xmm12,DWORD PTR [r14+r13*1+0x30]{1to4},0x2
  72:	0c 02 
  74:	62 83 7d 18 04 44 2e 	vpermilps xmm16,DWORD PTR [r14+r13*1+0x34]{1to4},0x2
  7b:	0d 02 
  7d:	62 83 7d 18 04 4c 2e 	vpermilps xmm17,DWORD PTR [r14+r13*1+0x38]{1to4},0x2
  84:	0e 02 
  86:	62 83 7d 18 04 54 2e 	vpermilps xmm18,DWORD PTR [r14+r13*1+0x3c]{1to4},0x2
  8d:	0f 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX;
MOV [R14+32], RAX;
MOV [R14+36], RAX;
MOV [R14+40], RAX;
MOV [R14+44], RAX;
MOV [R14+48], RAX;
MOV [R14+52], RAX;
MOV [R14+56], RAX;
MOV [R14+60], RAX

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 12.0
- UOPS_EXECUTED.THREAD: 32.02
- RETIRE_SLOTS: 31.99
- UOPS_MITE: 31.98
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 16.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.02

With loop_count=1000 and unroll_count=1

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02 
   8:	62 93 7d 18 04 4c 2e 	vpermilps xmm1,DWORD PTR [r14+r13*1+0x4]{1to4},0x2
   f:	01 02 
  11:	62 93 7d 18 04 54 2e 	vpermilps xmm2,DWORD PTR [r14+r13*1+0x8]{1to4},0x2
  18:	02 02 
  1a:	62 93 7d 18 04 5c 2e 	vpermilps xmm3,DWORD PTR [r14+r13*1+0xc]{1to4},0x2
  21:	03 02 
  23:	62 93 7d 18 04 64 2e 	vpermilps xmm4,DWORD PTR [r14+r13*1+0x10]{1to4},0x2
  2a:	04 02 
  2c:	62 93 7d 18 04 6c 2e 	vpermilps xmm5,DWORD PTR [r14+r13*1+0x14]{1to4},0x2
  33:	05 02 
  35:	62 93 7d 18 04 74 2e 	vpermilps xmm6,DWORD PTR [r14+r13*1+0x18]{1to4},0x2
  3c:	06 02 
  3e:	62 93 7d 18 04 7c 2e 	vpermilps xmm7,DWORD PTR [r14+r13*1+0x1c]{1to4},0x2
  45:	07 02 
  47:	62 13 7d 18 04 44 2e 	vpermilps xmm8,DWORD PTR [r14+r13*1+0x20]{1to4},0x2
  4e:	08 02 
  50:	62 13 7d 18 04 4c 2e 	vpermilps xmm9,DWORD PTR [r14+r13*1+0x24]{1to4},0x2
  57:	09 02 
  59:	62 13 7d 18 04 54 2e 	vpermilps xmm10,DWORD PTR [r14+r13*1+0x28]{1to4},0x2
  60:	0a 02 
  62:	62 13 7d 18 04 5c 2e 	vpermilps xmm11,DWORD PTR [r14+r13*1+0x2c]{1to4},0x2
  69:	0b 02 
  6b:	62 13 7d 18 04 64 2e 	vpermilps xmm12,DWORD PTR [r14+r13*1+0x30]{1to4},0x2
  72:	0c 02 
  74:	62 83 7d 18 04 44 2e 	vpermilps xmm16,DWORD PTR [r14+r13*1+0x34]{1to4},0x2
  7b:	0d 02 
  7d:	62 83 7d 18 04 4c 2e 	vpermilps xmm17,DWORD PTR [r14+r13*1+0x38]{1to4},0x2
  84:	0e 02 
  86:	62 83 7d 18 04 54 2e 	vpermilps xmm18,DWORD PTR [r14+r13*1+0x3c]{1to4},0x2
  8d:	0f 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX;
MOV [R14+32], RAX;
MOV [R14+36], RAX;
MOV [R14+40], RAX;
MOV [R14+44], RAX;
MOV [R14+48], RAX;
MOV [R14+52], RAX;
MOV [R14+56], RAX;
MOV [R14+60], RAX

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.01
- Reference cycles: 12.02
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.04
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 16.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 93 7d 18 04 04 2e 	vpermilps xmm0,DWORD PTR [r14+r13*1]{1to4},0x2
   7:	02 
   8:	62 93 7d 18 04 4c 2e 	vpermilps xmm1,DWORD PTR [r14+r13*1+0x4]{1to4},0x2
   f:	01 02 
  11:	62 93 7d 18 04 54 2e 	vpermilps xmm2,DWORD PTR [r14+r13*1+0x8]{1to4},0x2
  18:	02 02 
  1a:	62 93 7d 18 04 5c 2e 	vpermilps xmm3,DWORD PTR [r14+r13*1+0xc]{1to4},0x2
  21:	03 02 
  23:	62 93 7d 18 04 64 2e 	vpermilps xmm4,DWORD PTR [r14+r13*1+0x10]{1to4},0x2
  2a:	04 02 
  2c:	62 93 7d 18 04 6c 2e 	vpermilps xmm5,DWORD PTR [r14+r13*1+0x14]{1to4},0x2
  33:	05 02 
  35:	62 93 7d 18 04 74 2e 	vpermilps xmm6,DWORD PTR [r14+r13*1+0x18]{1to4},0x2
  3c:	06 02 
  3e:	62 93 7d 18 04 7c 2e 	vpermilps xmm7,DWORD PTR [r14+r13*1+0x1c]{1to4},0x2
  45:	07 02 
  47:	62 13 7d 18 04 44 2e 	vpermilps xmm8,DWORD PTR [r14+r13*1+0x20]{1to4},0x2
  4e:	08 02 
  50:	62 13 7d 18 04 4c 2e 	vpermilps xmm9,DWORD PTR [r14+r13*1+0x24]{1to4},0x2
  57:	09 02 
  59:	62 13 7d 18 04 54 2e 	vpermilps xmm10,DWORD PTR [r14+r13*1+0x28]{1to4},0x2
  60:	0a 02 
  62:	62 13 7d 18 04 5c 2e 	vpermilps xmm11,DWORD PTR [r14+r13*1+0x2c]{1to4},0x2
  69:	0b 02 
  6b:	62 13 7d 18 04 64 2e 	vpermilps xmm12,DWORD PTR [r14+r13*1+0x30]{1to4},0x2
  72:	0c 02 
  74:	62 83 7d 18 04 44 2e 	vpermilps xmm16,DWORD PTR [r14+r13*1+0x34]{1to4},0x2
  7b:	0d 02 
  7d:	62 83 7d 18 04 4c 2e 	vpermilps xmm17,DWORD PTR [r14+r13*1+0x38]{1to4},0x2
  84:	0e 02 
  86:	62 83 7d 18 04 54 2e 	vpermilps xmm18,DWORD PTR [r14+r13*1+0x3c]{1to4},0x2
  8d:	0f 02

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+8], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX;
MOV [R14+32], RAX;
MOV [R14+36], RAX;
MOV [R14+40], RAX;
MOV [R14+44], RAX;
MOV [R14+48], RAX;
MOV [R14+52], RAX;
MOV [R14+56], RAX;
MOV [R14+60], RAX

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.01
- Reference cycles: 12.02
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.29
- UOPS_MS: 0.04
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 16.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.15

VPERMILPS_EVEX (XMM, M32_1to4, I8) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With unroll_count=500, no inner loop, and 5 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With unroll_count=500, no inner loop, and 5 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10