NOP - Throughput and Uops
With unroll_count=500 and no inner loop
Code:
0: 90 nop
Show nanoBench command
Results:
Instructions retired: 1.0
Core cycles: 0.13
Reference cycles: 0.1
UOPS_EXECUTED.THREAD: 0.0
RETIRE_SLOTS: 1.0
UOPS_MITE: 1.0
UOPS_MS: 0.0
UOPS_DISPATCHED.INT_EU_ALL: 0.0
UOPS_DISPATCHED.ALU: 0.0
UOPS_DISPATCHED.SLOW: 0.0
UOPS_DISPATCHED.STD: 0.0
UOPS_DISPATCHED.SHIFT: 0.0
UOPS_DISPATCHED.JMP: 0.0
UOPS_DISPATCHED.STA: 0.0
UOPS_DISPATCHED.V0: 0.0
UOPS_DISPATCHED.V1: 0.0
UOPS_DISPATCHED.V2: 0.0
UOPS_DISPATCHED.V3: 0.0
DIV_CYCLES: 0.0
ILD_STALL.LCP: 0.0
UOPS_MITE>=1: 0.13
With loop_count=1000 and unroll_count=10
Code:
0: 90 nop
Show nanoBench command
Results:
Instructions retired: 1.2
Core cycles: 0.14
Reference cycles: 0.09
UOPS_EXECUTED.THREAD: 0.1
RETIRE_SLOTS: 1.1
UOPS_MITE: 0.0
UOPS_MS: 0.0
UOPS_DISPATCHED.INT_EU_ALL: 0.1
UOPS_DISPATCHED.ALU: 0.0
UOPS_DISPATCHED.SLOW: 0.0
UOPS_DISPATCHED.STD: 0.0
UOPS_DISPATCHED.SHIFT: 0.0
UOPS_DISPATCHED.JMP: 0.1
UOPS_DISPATCHED.STA: 0.0
UOPS_DISPATCHED.V0: 0.0
UOPS_DISPATCHED.V1: 0.0
UOPS_DISPATCHED.V2: 0.0
UOPS_DISPATCHED.V3: 0.0
DIV_CYCLES: 0.0
ILD_STALL.LCP: 0.0
UOPS_MITE>=1: 0.0
With loop_count=1000, unroll_count=10, and padding (redundant prefixes)
Code:
0: 40 rex 1: 40 rex 2: 40 rex 3: 40 rex 4: 40 rex 5: 40 rex 6: 40 90 rex nop
Show nanoBench command
Results:
Instructions retired: 1.2
Core cycles: 0.14
Reference cycles: 0.1
UOPS_EXECUTED.THREAD: 0.1
RETIRE_SLOTS: 1.1
UOPS_MITE: 0.0
UOPS_MS: 0.0
UOPS_DISPATCHED.INT_EU_ALL: 0.1
UOPS_DISPATCHED.ALU: 0.0
UOPS_DISPATCHED.SLOW: 0.0
UOPS_DISPATCHED.STD: 0.0
UOPS_DISPATCHED.SHIFT: 0.0
UOPS_DISPATCHED.JMP: 0.1
UOPS_DISPATCHED.STA: 0.0
UOPS_DISPATCHED.V0: 0.0
UOPS_DISPATCHED.V1: 0.0
UOPS_DISPATCHED.V2: 0.0
UOPS_DISPATCHED.V3: 0.0
DIV_CYCLES: 0.0
ILD_STALL.LCP: 0.0
UOPS_MITE>=1: 0.0
With loop_count=100 and unroll_count=100
Code:
0: 90 nop
Show nanoBench command
Results:
Instructions retired: 1.02
Core cycles: 0.13
Reference cycles: 0.09
UOPS_EXECUTED.THREAD: 0.01
RETIRE_SLOTS: 1.01
UOPS_MITE: 0.25
UOPS_MS: 0.0
UOPS_DISPATCHED.INT_EU_ALL: 0.01
UOPS_DISPATCHED.ALU: 0.0
UOPS_DISPATCHED.SLOW: 0.0
UOPS_DISPATCHED.STD: 0.0
UOPS_DISPATCHED.SHIFT: 0.0
UOPS_DISPATCHED.JMP: 0.01
UOPS_DISPATCHED.STA: 0.0
UOPS_DISPATCHED.V0: 0.0
UOPS_DISPATCHED.V1: 0.0
UOPS_DISPATCHED.V2: 0.0
UOPS_DISPATCHED.V3: 0.0
DIV_CYCLES: 0.0
ILD_STALL.LCP: 0.0
UOPS_MITE>=1: 0.03
With loop_count=100, unroll_count=100, and padding (redundant prefixes)
Code:
0: 40 rex 1: 40 rex 2: 40 rex 3: 40 rex 4: 40 rex 5: 40 rex 6: 40 90 rex nop
Show nanoBench command
Results:
Instructions retired: 1.02
Core cycles: 0.13
Reference cycles: 0.1
UOPS_EXECUTED.THREAD: 0.01
RETIRE_SLOTS: 1.01
UOPS_MITE: 0.01
UOPS_MS: 0.0
UOPS_DISPATCHED.INT_EU_ALL: 0.01
UOPS_DISPATCHED.ALU: 0.0
UOPS_DISPATCHED.SLOW: 0.0
UOPS_DISPATCHED.STD: 0.0
UOPS_DISPATCHED.SHIFT: 0.0
UOPS_DISPATCHED.JMP: 0.01
UOPS_DISPATCHED.STA: 0.0
UOPS_DISPATCHED.V0: 0.0
UOPS_DISPATCHED.V1: 0.0
UOPS_DISPATCHED.V2: 0.0
UOPS_DISPATCHED.V3: 0.0
DIV_CYCLES: 0.0
ILD_STALL.LCP: 0.0
UOPS_MITE>=1: 0.0