CMPXCHG_LOCK (M16, R16) - Throughput and Uops (IACA 2.2)
With a non-indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 7.00 Cycles Throughput Bottleneck: Dependency chains (possibly between iterations)
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 2.0 0.0 | 1.5 | 0.6 0.5 | 0.7 0.5 | 1.0 | 1.5 | 2.0 | 0.6 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 10^ | 2.0 | 1.5 | 0.6 0.5 | 0.7 0.5 | 1.0 | 1.5 | 2.0 | 0.6 | CP | lock cmpxchg word ptr [r14], r8w
Total Num Of Uops: 10
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 2.25 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 2.0 0.0 | 1.5 | 0.6 0.5 | 0.8 0.5 | 1.0 | 1.5 | 2.0 | 0.6 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 10^ | 2.0 | 1.5 | 0.6 0.5 | 0.8 0.5 | 1.0 | 1.5 | 2.0 | 0.6 | | lock cmpxchg word ptr [r14], r8w
| 1* | | | | | | | | | | xor rax, rax
Total Num Of Uops: 11
With 16 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 112.00 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 32.0 0.0 | 24.0 | 10.7 8.0 | 10.6 8.0 | 16.0 | 24.0 | 32.0 | 10.6 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 10^ | 2.0 | 1.0 | 1.0 1.0 | 0.3 | 1.0 | 2.0 | 2.0 | 0.6 | | lock cmpxchg word ptr [r14], r8w
| 10^ | 2.0 | 2.0 | 0.3 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 0.6 | | lock cmpxchg word ptr [r14+0x2], r8w
| 10^ | 2.0 | 1.0 | 1.0 1.0 | 0.3 | 1.0 | 2.0 | 2.0 | 0.7 | | lock cmpxchg word ptr [r14+0x4], r8w
| 10^ | 2.0 | 2.0 | 0.3 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 0.6 | | lock cmpxchg word ptr [r14+0x6], r8w
| 10^ | 2.0 | 1.0 | 1.0 1.0 | 0.3 | 1.0 | 2.0 | 2.0 | 0.6 | | lock cmpxchg word ptr [r14+0x8], r8w
| 10^ | 2.0 | 2.0 | 0.3 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 0.7 | | lock cmpxchg word ptr [r14+0xa], r8w
| 10^ | 2.0 | 1.0 | 1.0 1.0 | 0.3 | 1.0 | 2.0 | 2.0 | 0.6 | | lock cmpxchg word ptr [r14+0xc], r8w
| 10^ | 2.0 | 2.0 | 0.3 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 0.6 | | lock cmpxchg word ptr [r14+0xe], r8w
| 10^ | 2.0 | 1.0 | 1.0 1.0 | 0.3 | 1.0 | 2.0 | 2.0 | 0.7 | | lock cmpxchg word ptr [r14+0x10], r8w
| 10^ | 2.0 | 2.0 | 0.3 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 0.6 | | lock cmpxchg word ptr [r14+0x12], r8w
| 10^ | 2.0 | 1.0 | 1.0 1.0 | 0.3 | 1.0 | 2.0 | 2.0 | 0.6 | | lock cmpxchg word ptr [r14+0x14], r8w
| 10^ | 2.0 | 2.0 | 0.3 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 0.7 | | lock cmpxchg word ptr [r14+0x16], r8w
| 10^ | 2.0 | 1.0 | 1.0 1.0 | 0.3 | 1.0 | 2.0 | 2.0 | 0.6 | | lock cmpxchg word ptr [r14+0x18], r8w
| 10^ | 2.0 | 2.0 | 0.3 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 0.6 | | lock cmpxchg word ptr [r14+0x1a], r8w
| 10^ | 2.0 | 1.0 | 1.0 1.0 | 0.3 | 1.0 | 2.0 | 2.0 | 0.7 | | lock cmpxchg word ptr [r14+0x1c], r8w
| 10^ | 2.0 | 2.0 | 0.3 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 0.6 | | lock cmpxchg word ptr [r14+0x1e], r8w
Total Num Of Uops: 160
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 36.00 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 32.0 0.0 | 24.0 | 10.0 8.0 | 12.0 8.0 | 16.0 | 24.0 | 32.0 | 10.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 10^ | 2.0 | 1.0 | 1.0 1.0 | | 1.0 | 2.0 | 2.0 | 1.0 | | lock cmpxchg word ptr [r14], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+0x2], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 1.0 1.0 | | 1.0 | 2.0 | 2.0 | 1.0 | | lock cmpxchg word ptr [r14+0x4], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 2.0 | | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 1.0 | | lock cmpxchg word ptr [r14+0x6], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+0x8], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 2.0 | | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 1.0 | | lock cmpxchg word ptr [r14+0xa], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+0xc], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 2.0 | | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 1.0 | | lock cmpxchg word ptr [r14+0xe], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 1.0 1.0 | | 1.0 | 2.0 | 2.0 | 1.0 | | lock cmpxchg word ptr [r14+0x10], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+0x12], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 1.0 1.0 | | 1.0 | 2.0 | 2.0 | 1.0 | | lock cmpxchg word ptr [r14+0x14], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 2.0 | | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 1.0 | | lock cmpxchg word ptr [r14+0x16], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+0x18], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 2.0 | | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 1.0 | | lock cmpxchg word ptr [r14+0x1a], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+0x1c], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 2.0 | | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 1.0 | | lock cmpxchg word ptr [r14+0x1e], r8w
| 1* | | | | | | | | | | xor rax, rax
Total Num Of Uops: 176
With an indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 7.00 Cycles Throughput Bottleneck: Dependency chains (possibly between iterations)
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 2.0 0.0 | 1.5 | 1.0 0.5 | 1.0 0.5 | 1.0 | 1.5 | 2.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 10 | 2.0 | 1.5 | 1.0 0.5 | 1.0 0.5 | 1.0 | 1.5 | 2.0 | | CP | lock cmpxchg word ptr [r14+r13*1], r8w
Total Num Of Uops: 10
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 2.75 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 2.0 0.0 | 1.5 | 1.0 0.5 | 1.0 0.5 | 1.0 | 1.5 | 2.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 10 | 2.0 | 1.5 | 1.0 0.5 | 1.0 0.5 | 1.0 | 1.5 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1], r8w
| 1* | | | | | | | | | | xor rax, rax
Total Num Of Uops: 11
With 16 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 112.00 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 32.0 0.0 | 24.0 | 16.0 8.0 | 16.0 8.0 | 16.0 | 24.0 | 32.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1], r8w
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x2], r8w
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x4], r8w
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x6], r8w
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x8], r8w
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0xa], r8w
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0xc], r8w
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0xe], r8w
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x10], r8w
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x12], r8w
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x14], r8w
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x16], r8w
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x18], r8w
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x1a], r8w
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x1c], r8w
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x1e], r8w
Total Num Of Uops: 160
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 44.00 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 32.0 0.0 | 24.0 | 16.0 8.0 | 16.0 8.0 | 16.0 | 24.0 | 32.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x2], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x4], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x6], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x8], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0xa], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0xc], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0xe], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x10], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x12], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x14], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x16], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x18], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x1a], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x1c], r8w
| 1* | | | | | | | | | | xor rax, rax
| 10 | 2.0 | 2.0 | 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | | lock cmpxchg word ptr [r14+r13*1+0x1e], r8w
| 1* | | | | | | | | | | xor rax, rax
Total Num Of Uops: 176
With the -no_interiteration flag
Throughput Analysis Report
--------------------------
Block Throughput: 5.24 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 2.0 0.0 | 1.5 | 0.6 0.5 | 0.7 0.5 | 1.0 | 1.5 | 2.0 | 0.6 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 10^ | 2.0 | 1.5 | 0.6 0.5 | 0.7 0.5 | 1.0 | 1.5 | 2.0 | 0.6 | | lock cmpxchg word ptr [r14], r8w
Total Num Of Uops: 10