MUL (R64) - Throughput and Uops
With unroll_count=500 and no inner loop
Code:
0: 49 f7 e0 mul r8
Show nanoBench command
Results:
Instructions retired: 1.0
Core cycles: 7.0
Reference cycles: 7.01
RS_UOPS_DISPATCHED: 3.0
UOPS_PORT_0: 2.0
UOPS_PORT_1: 0.51
UOPS_PORT_2: 0.0
UOPS_PORT_3: 0.0
UOPS_PORT_4: 0.0
UOPS_PORT_5: 0.49
With loop_count=1000 and unroll_count=10
Code:
0: 49 f7 e0 mul r8
Show nanoBench command
Results:
Instructions retired: 1.2
Core cycles: 6.8
Reference cycles: 6.8
RS_UOPS_DISPATCHED: 3.2
UOPS_PORT_0: 2.0
UOPS_PORT_1: 0.5
UOPS_PORT_2: 0.0
UOPS_PORT_3: 0.0
UOPS_PORT_4: 0.0
UOPS_PORT_5: 0.7
With loop_count=100 and unroll_count=100
Code:
0: 49 f7 e0 mul r8
Show nanoBench command
Results:
Instructions retired: 1.02
Core cycles: 6.9
Reference cycles: 6.9
RS_UOPS_DISPATCHED: 3.02
UOPS_PORT_0: 2.0
UOPS_PORT_1: 0.51
UOPS_PORT_2: 0.0
UOPS_PORT_3: 0.0
UOPS_PORT_4: 0.0
UOPS_PORT_5: 0.51
With additional dependency-breaking instructions
With unroll_count=500 and no inner loop
Code:
0: 48 31 c0 xor rax,rax 3: 49 f7 e0 mul r8
Show nanoBench command
Results:
Instructions retired: 2.0
Core cycles: 4.0
Reference cycles: 4.0
RS_UOPS_DISPATCHED: 4.0
UOPS_PORT_0: 2.0
UOPS_PORT_1: 1.0
UOPS_PORT_2: 0.0
UOPS_PORT_3: 0.0
UOPS_PORT_4: 0.0
UOPS_PORT_5: 1.0
With loop_count=1000 and unroll_count=10
Code:
0: 48 31 c0 xor rax,rax 3: 49 f7 e0 mul r8
Show nanoBench command
Results:
Instructions retired: 2.2
Core cycles: 4.0
Reference cycles: 4.0
RS_UOPS_DISPATCHED: 4.2
UOPS_PORT_0: 2.0
UOPS_PORT_1: 0.95
UOPS_PORT_2: 0.0
UOPS_PORT_3: 0.0
UOPS_PORT_4: 0.0
UOPS_PORT_5: 1.25
With loop_count=100 and unroll_count=100
Code:
0: 48 31 c0 xor rax,rax 3: 49 f7 e0 mul r8
Show nanoBench command
Results:
Instructions retired: 2.02
Core cycles: 4.0
Reference cycles: 4.0
RS_UOPS_DISPATCHED: 4.02
UOPS_PORT_0: 2.0
UOPS_PORT_1: 1.01
UOPS_PORT_2: 0.0
UOPS_PORT_3: 0.0
UOPS_PORT_4: 0.0
UOPS_PORT_5: 1.02