ADD (M32, R32)

With unroll_count=500 and no inner loop

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 7.36
- Reference cycles: 4.29
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 1.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.77
- UOPS_PORT_1: 2.78
- UOPS_PORT_6: 2.83
- UOPS_PORT_49: 6.04
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 6.0
- UOPS_PORT_5B>=2: 1.32
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 7.4
- Reference cycles: 4.37
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 2.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.96
- UOPS_PORT_1: 2.83
- UOPS_PORT_6: 2.89
- UOPS_PORT_49: 5.86
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 5.54
- UOPS_PORT_5B>=2: 0.78
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	90                   	nop
   4:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 7.34
- Reference cycles: 4.32
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 3.98
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.04
- UOPS_PORT_1: 2.26
- UOPS_PORT_6: 2.5
- UOPS_PORT_49: 4.63
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 4.87
- UOPS_PORT_5B>=2: 0.82
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	90                   	nop
   4:	90                   	nop
   5:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 7.36
- Reference cycles: 4.37
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.53
- UOPS_PORT_1: 2.64
- UOPS_PORT_6: 2.87
- UOPS_PORT_49: 6.5
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 5.82
- UOPS_PORT_5B>=2: 1.27
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	90                   	nop
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 7.43
- Reference cycles: 4.4
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.53
- UOPS_PORT_1: 2.79
- UOPS_PORT_6: 2.83
- UOPS_PORT_49: 3.75
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 5.46
- UOPS_PORT_5B>=2: 0.68
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 5 NOPs

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	90                   	nop
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.4
- Reference cycles: 4.45
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 6.98
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.69
- UOPS_PORT_1: 2.75
- UOPS_PORT_6: 2.9
- UOPS_PORT_49: 4.85
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 5.48
- UOPS_PORT_5B>=2: 1.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.99

With loop_count=1000 and unroll_count=10

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 7.36
- Reference cycles: 4.33
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.07
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.81
- UOPS_PORT_1: 2.86
- UOPS_PORT_6: 3.1
- UOPS_PORT_49: 6.91
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 5.96
- UOPS_PORT_5B>=2: 1.18
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	45 01 06             	add    DWORD PTR [r14],r8d

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 7.37
- Reference cycles: 4.34
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.83
- UOPS_PORT_1: 2.92
- UOPS_PORT_6: 3.14
- UOPS_PORT_49: 6.28
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 5.86
- UOPS_PORT_5B>=2: 1.17
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 7.34
- Reference cycles: 4.33
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 2.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.92
- UOPS_PORT_1: 3.0
- UOPS_PORT_6: 2.96
- UOPS_PORT_49: 7.19
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 6.14
- UOPS_PORT_5B>=2: 1.28
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	45 01 06             	add    DWORD PTR [r14],r8d

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 7.37
- Reference cycles: 4.34
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.8
- UOPS_PORT_1: 2.9
- UOPS_PORT_6: 2.86
- UOPS_PORT_49: 6.54
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 5.98
- UOPS_PORT_5B>=2: 1.22
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 01 46 04          	add    DWORD PTR [r14+0x4],r8d
   7:	45 01 46 08          	add    DWORD PTR [r14+0x8],r8d
   b:	45 01 46 0c          	add    DWORD PTR [r14+0xc],r8d

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 7.73
- Reference cycles: 4.4
- UOPS_EXECUTED.THREAD: 15.98
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 7.94
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.2
- UOPS_PORT_1: 3.21
- UOPS_PORT_6: 3.34
- UOPS_PORT_49: 6.51
- UOPS_PORT_78: 4.0
- UOPS_PORT_5B: 7.06
- UOPS_PORT_5B>=2: 1.5
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.98

With loop_count=1000 and unroll_count=2

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 01 46 04          	add    DWORD PTR [r14+0x4],r8d
   7:	45 01 46 08          	add    DWORD PTR [r14+0x8],r8d
   b:	45 01 46 0c          	add    DWORD PTR [r14+0xc],r8d

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 8.23
- Reference cycles: 4.88
- UOPS_EXECUTED.THREAD: 16.55
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.26
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.81
- UOPS_PORT_1: 2.84
- UOPS_PORT_6: 3.28
- UOPS_PORT_49: 5.41
- UOPS_PORT_78: 4.01
- UOPS_PORT_5B: 6.14
- UOPS_PORT_5B>=2: 1.18
- UOPS_PORT_23A: 4.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.13

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	45 01 06             	add    DWORD PTR [r14],r8d
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	45 01 46 04          	add    DWORD PTR [r14+0x4],r8d
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	45 01 46 08          	add    DWORD PTR [r14+0x8],r8d
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	45 01 46 0c          	add    DWORD PTR [r14+0xc],r8d

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 7.99
- Reference cycles: 4.72
- UOPS_EXECUTED.THREAD: 16.53
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.43
- UOPS_PORT_1: 3.42
- UOPS_PORT_6: 3.89
- UOPS_PORT_49: 5.7
- UOPS_PORT_78: 4.01
- UOPS_PORT_5B: 7.2
- UOPS_PORT_5B>=2: 1.51
- UOPS_PORT_23A: 4.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 01 46 04          	add    DWORD PTR [r14+0x4],r8d
   7:	45 01 46 08          	add    DWORD PTR [r14+0x8],r8d
   b:	45 01 46 0c          	add    DWORD PTR [r14+0xc],r8d

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 7.39
- Reference cycles: 4.35
- UOPS_EXECUTED.THREAD: 16.08
- RETIRE_SLOTS: 8.06
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.87
- UOPS_PORT_1: 2.9
- UOPS_PORT_6: 2.98
- UOPS_PORT_49: 5.75
- UOPS_PORT_78: 4.0
- UOPS_PORT_5B: 6.71
- UOPS_PORT_5B>=2: 1.32
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	45 01 06             	add    DWORD PTR [r14],r8d
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	45 01 46 04          	add    DWORD PTR [r14+0x4],r8d
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	45 01 46 08          	add    DWORD PTR [r14+0x8],r8d
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	45 01 46 0c          	add    DWORD PTR [r14+0xc],r8d

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 7.59
- Reference cycles: 4.45
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.26
- UOPS_PORT_1: 3.26
- UOPS_PORT_6: 3.36
- UOPS_PORT_49: 6.18
- UOPS_PORT_78: 4.0
- UOPS_PORT_5B: 6.65
- UOPS_PORT_5B>=2: 1.33
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 01 46 04          	add    DWORD PTR [r14+0x4],r8d
   7:	45 01 46 08          	add    DWORD PTR [r14+0x8],r8d
   b:	45 01 46 0c          	add    DWORD PTR [r14+0xc],r8d
   f:	45 01 46 10          	add    DWORD PTR [r14+0x10],r8d
  13:	45 01 46 14          	add    DWORD PTR [r14+0x14],r8d
  17:	45 01 46 18          	add    DWORD PTR [r14+0x18],r8d
  1b:	45 01 46 1c          	add    DWORD PTR [r14+0x1c],r8d

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 7.7
- Reference cycles: 4.53
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.05
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.66
- UOPS_PORT_1: 3.75
- UOPS_PORT_6: 3.9
- UOPS_PORT_49: 9.38
- UOPS_PORT_78: 8.0
- UOPS_PORT_5B: 8.09
- UOPS_PORT_5B>=2: 1.8
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.02

With loop_count=1000 and unroll_count=1

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 01 46 04          	add    DWORD PTR [r14+0x4],r8d
   7:	45 01 46 08          	add    DWORD PTR [r14+0x8],r8d
   b:	45 01 46 0c          	add    DWORD PTR [r14+0xc],r8d
   f:	45 01 46 10          	add    DWORD PTR [r14+0x10],r8d
  13:	45 01 46 14          	add    DWORD PTR [r14+0x14],r8d
  17:	45 01 46 18          	add    DWORD PTR [r14+0x18],r8d
  1b:	45 01 46 1c          	add    DWORD PTR [r14+0x1c],r8d

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 7.68
- Reference cycles: 4.49
- UOPS_EXECUTED.THREAD: 33.04
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 4.72
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.57
- UOPS_PORT_1: 3.63
- UOPS_PORT_6: 4.39
- UOPS_PORT_49: 9.21
- UOPS_PORT_78: 8.02
- UOPS_PORT_5B: 7.42
- UOPS_PORT_5B>=2: 1.68
- UOPS_PORT_23A: 8.03
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.16

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	45 01 06             	add    DWORD PTR [r14],r8d
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	45 01 46 04          	add    DWORD PTR [r14+0x4],r8d
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	45 01 46 08          	add    DWORD PTR [r14+0x8],r8d
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	45 01 46 0c          	add    DWORD PTR [r14+0xc],r8d
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	40                   	rex
  28:	45 01 46 10          	add    DWORD PTR [r14+0x10],r8d
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	45 01 46 14          	add    DWORD PTR [r14+0x14],r8d
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	40                   	rex
  3a:	45 01 46 18          	add    DWORD PTR [r14+0x18],r8d
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	45 01 46 1c          	add    DWORD PTR [r14+0x1c],r8d

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 7.63
- Reference cycles: 4.48
- UOPS_EXECUTED.THREAD: 33.08
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.99
- UOPS_PORT_1: 4.04
- UOPS_PORT_6: 4.77
- UOPS_PORT_49: 9.45
- UOPS_PORT_78: 8.03
- UOPS_PORT_5B: 8.29
- UOPS_PORT_5B>=2: 2.09
- UOPS_PORT_23A: 8.04
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 01 46 04          	add    DWORD PTR [r14+0x4],r8d
   7:	45 01 46 08          	add    DWORD PTR [r14+0x8],r8d
   b:	45 01 46 0c          	add    DWORD PTR [r14+0xc],r8d
   f:	45 01 46 10          	add    DWORD PTR [r14+0x10],r8d
  13:	45 01 46 14          	add    DWORD PTR [r14+0x14],r8d
  17:	45 01 46 18          	add    DWORD PTR [r14+0x18],r8d
  1b:	45 01 46 1c          	add    DWORD PTR [r14+0x1c],r8d

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 7.36
- Reference cycles: 4.32
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.17
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.01
- UOPS_PORT_1: 4.03
- UOPS_PORT_6: 4.15
- UOPS_PORT_49: 9.52
- UOPS_PORT_78: 8.0
- UOPS_PORT_5B: 8.12
- UOPS_PORT_5B>=2: 1.95
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	45 01 06             	add    DWORD PTR [r14],r8d
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	45 01 46 04          	add    DWORD PTR [r14+0x4],r8d
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	45 01 46 08          	add    DWORD PTR [r14+0x8],r8d
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	45 01 46 0c          	add    DWORD PTR [r14+0xc],r8d
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	40                   	rex
  28:	45 01 46 10          	add    DWORD PTR [r14+0x10],r8d
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	45 01 46 14          	add    DWORD PTR [r14+0x14],r8d
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	40                   	rex
  3a:	45 01 46 18          	add    DWORD PTR [r14+0x18],r8d
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	45 01 46 1c          	add    DWORD PTR [r14+0x1c],r8d

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 7.41
- Reference cycles: 4.36
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.17
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.99
- UOPS_PORT_1: 3.99
- UOPS_PORT_6: 4.14
- UOPS_PORT_49: 9.51
- UOPS_PORT_78: 8.0
- UOPS_PORT_5B: 8.11
- UOPS_PORT_5B>=2: 1.94
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 01 46 04          	add    DWORD PTR [r14+0x4],r8d
   7:	45 01 46 08          	add    DWORD PTR [r14+0x8],r8d
   b:	45 01 46 0c          	add    DWORD PTR [r14+0xc],r8d
   f:	45 01 46 10          	add    DWORD PTR [r14+0x10],r8d
  13:	45 01 46 14          	add    DWORD PTR [r14+0x14],r8d
  17:	45 01 46 18          	add    DWORD PTR [r14+0x18],r8d
  1b:	45 01 46 1c          	add    DWORD PTR [r14+0x1c],r8d
  1f:	45 01 46 20          	add    DWORD PTR [r14+0x20],r8d
  23:	45 01 46 24          	add    DWORD PTR [r14+0x24],r8d
  27:	45 01 46 28          	add    DWORD PTR [r14+0x28],r8d
  2b:	45 01 46 2c          	add    DWORD PTR [r14+0x2c],r8d
  2f:	45 01 46 30          	add    DWORD PTR [r14+0x30],r8d
  33:	45 01 46 34          	add    DWORD PTR [r14+0x34],r8d
  37:	45 01 46 38          	add    DWORD PTR [r14+0x38],r8d
  3b:	45 01 46 3c          	add    DWORD PTR [r14+0x3c],r8d

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 9.6
- UOPS_EXECUTED.THREAD: 64.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.21
- UOPS_PORT_1: 3.23
- UOPS_PORT_6: 3.19
- UOPS_PORT_49: 16.0
- UOPS_PORT_78: 16.0
- UOPS_PORT_5B: 6.4
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 01 46 04          	add    DWORD PTR [r14+0x4],r8d
   7:	45 01 46 08          	add    DWORD PTR [r14+0x8],r8d
   b:	45 01 46 0c          	add    DWORD PTR [r14+0xc],r8d
   f:	45 01 46 10          	add    DWORD PTR [r14+0x10],r8d
  13:	45 01 46 14          	add    DWORD PTR [r14+0x14],r8d
  17:	45 01 46 18          	add    DWORD PTR [r14+0x18],r8d
  1b:	45 01 46 1c          	add    DWORD PTR [r14+0x1c],r8d
  1f:	45 01 46 20          	add    DWORD PTR [r14+0x20],r8d
  23:	45 01 46 24          	add    DWORD PTR [r14+0x24],r8d
  27:	45 01 46 28          	add    DWORD PTR [r14+0x28],r8d
  2b:	45 01 46 2c          	add    DWORD PTR [r14+0x2c],r8d
  2f:	45 01 46 30          	add    DWORD PTR [r14+0x30],r8d
  33:	45 01 46 34          	add    DWORD PTR [r14+0x34],r8d
  37:	45 01 46 38          	add    DWORD PTR [r14+0x38],r8d
  3b:	45 01 46 3c          	add    DWORD PTR [r14+0x3c],r8d

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 10.1
- Reference cycles: 5.95
- UOPS_EXECUTED.THREAD: 65.02
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.76
- UOPS_PORT_1: 4.8
- UOPS_PORT_6: 5.53
- UOPS_PORT_49: 16.01
- UOPS_PORT_78: 16.01
- UOPS_PORT_5B: 9.86
- UOPS_PORT_5B>=2: 2.55
- UOPS_PORT_23A: 16.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	45 01 06             	add    DWORD PTR [r14],r8d
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	45 01 46 04          	add    DWORD PTR [r14+0x4],r8d
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	45 01 46 08          	add    DWORD PTR [r14+0x8],r8d
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	45 01 46 0c          	add    DWORD PTR [r14+0xc],r8d
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	40                   	rex
  28:	45 01 46 10          	add    DWORD PTR [r14+0x10],r8d
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	45 01 46 14          	add    DWORD PTR [r14+0x14],r8d
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	40                   	rex
  3a:	45 01 46 18          	add    DWORD PTR [r14+0x18],r8d
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	45 01 46 1c          	add    DWORD PTR [r14+0x1c],r8d
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	45 01 46 20          	add    DWORD PTR [r14+0x20],r8d
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	40                   	rex
  55:	45 01 46 24          	add    DWORD PTR [r14+0x24],r8d
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	40                   	rex
  5d:	40                   	rex
  5e:	45 01 46 28          	add    DWORD PTR [r14+0x28],r8d
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	40                   	rex
  67:	45 01 46 2c          	add    DWORD PTR [r14+0x2c],r8d
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	40                   	rex
  6f:	40                   	rex
  70:	45 01 46 30          	add    DWORD PTR [r14+0x30],r8d
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	40                   	rex
  79:	45 01 46 34          	add    DWORD PTR [r14+0x34],r8d
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	40                   	rex
  81:	40                   	rex
  82:	45 01 46 38          	add    DWORD PTR [r14+0x38],r8d
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	40                   	rex
  8b:	45 01 46 3c          	add    DWORD PTR [r14+0x3c],r8d

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 10.06
- Reference cycles: 5.91
- UOPS_EXECUTED.THREAD: 65.02
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.76
- UOPS_PORT_1: 4.81
- UOPS_PORT_6: 5.54
- UOPS_PORT_49: 16.01
- UOPS_PORT_78: 16.01
- UOPS_PORT_5B: 9.87
- UOPS_PORT_5B>=2: 2.54
- UOPS_PORT_23A: 16.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	45 01 06             	add    DWORD PTR [r14],r8d
   3:	45 01 46 04          	add    DWORD PTR [r14+0x4],r8d
   7:	45 01 46 08          	add    DWORD PTR [r14+0x8],r8d
   b:	45 01 46 0c          	add    DWORD PTR [r14+0xc],r8d
   f:	45 01 46 10          	add    DWORD PTR [r14+0x10],r8d
  13:	45 01 46 14          	add    DWORD PTR [r14+0x14],r8d
  17:	45 01 46 18          	add    DWORD PTR [r14+0x18],r8d
  1b:	45 01 46 1c          	add    DWORD PTR [r14+0x1c],r8d
  1f:	45 01 46 20          	add    DWORD PTR [r14+0x20],r8d
  23:	45 01 46 24          	add    DWORD PTR [r14+0x24],r8d
  27:	45 01 46 28          	add    DWORD PTR [r14+0x28],r8d
  2b:	45 01 46 2c          	add    DWORD PTR [r14+0x2c],r8d
  2f:	45 01 46 30          	add    DWORD PTR [r14+0x30],r8d
  33:	45 01 46 34          	add    DWORD PTR [r14+0x34],r8d
  37:	45 01 46 38          	add    DWORD PTR [r14+0x38],r8d
  3b:	45 01 46 3c          	add    DWORD PTR [r14+0x3c],r8d

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 9.96
- Reference cycles: 5.84
- UOPS_EXECUTED.THREAD: 64.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.74
- UOPS_PORT_1: 4.78
- UOPS_PORT_6: 4.95
- UOPS_PORT_49: 16.01
- UOPS_PORT_78: 16.0
- UOPS_PORT_5B: 9.75
- UOPS_PORT_5B>=2: 2.43
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	45 01 06             	add    DWORD PTR [r14],r8d
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	45 01 46 04          	add    DWORD PTR [r14+0x4],r8d
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	45 01 46 08          	add    DWORD PTR [r14+0x8],r8d
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	45 01 46 0c          	add    DWORD PTR [r14+0xc],r8d
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	40                   	rex
  28:	45 01 46 10          	add    DWORD PTR [r14+0x10],r8d
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	45 01 46 14          	add    DWORD PTR [r14+0x14],r8d
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	40                   	rex
  3a:	45 01 46 18          	add    DWORD PTR [r14+0x18],r8d
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	45 01 46 1c          	add    DWORD PTR [r14+0x1c],r8d
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	45 01 46 20          	add    DWORD PTR [r14+0x20],r8d
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	40                   	rex
  55:	45 01 46 24          	add    DWORD PTR [r14+0x24],r8d
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	40                   	rex
  5d:	40                   	rex
  5e:	45 01 46 28          	add    DWORD PTR [r14+0x28],r8d
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	40                   	rex
  67:	45 01 46 2c          	add    DWORD PTR [r14+0x2c],r8d
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	40                   	rex
  6f:	40                   	rex
  70:	45 01 46 30          	add    DWORD PTR [r14+0x30],r8d
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	40                   	rex
  79:	45 01 46 34          	add    DWORD PTR [r14+0x34],r8d
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	40                   	rex
  81:	40                   	rex
  82:	45 01 46 38          	add    DWORD PTR [r14+0x38],r8d
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	40                   	rex
  8b:	45 01 46 3c          	add    DWORD PTR [r14+0x3c],r8d

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 9.95
- Reference cycles: 5.88
- UOPS_EXECUTED.THREAD: 64.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.37
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.76
- UOPS_PORT_1: 4.78
- UOPS_PORT_6: 4.95
- UOPS_PORT_49: 16.01
- UOPS_PORT_78: 16.0
- UOPS_PORT_5B: 9.74
- UOPS_PORT_5B>=2: 2.44
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.17

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 7.39
- Reference cycles: 4.48
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 1.98
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.85
- UOPS_PORT_1: 2.58
- UOPS_PORT_6: 2.93
- UOPS_PORT_49: 5.84
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 5.87
- UOPS_PORT_5B>=2: 1.35
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 7.44
- Reference cycles: 4.37
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 2.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.5
- UOPS_PORT_1: 2.79
- UOPS_PORT_6: 2.8
- UOPS_PORT_49: 4.06
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 5.58
- UOPS_PORT_5B>=2: 0.83
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	90                   	nop
   5:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 7.44
- Reference cycles: 4.37
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 3.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.5
- UOPS_PORT_1: 2.79
- UOPS_PORT_6: 2.8
- UOPS_PORT_49: 4.05
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 5.58
- UOPS_PORT_5B>=2: 0.83
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 7.36
- Reference cycles: 4.4
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.63
- UOPS_PORT_1: 2.78
- UOPS_PORT_6: 2.89
- UOPS_PORT_49: 4.24
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 4.36
- UOPS_PORT_5B>=2: 0.6
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 7.39
- Reference cycles: 4.32
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 5.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.62
- UOPS_PORT_1: 2.67
- UOPS_PORT_6: 2.59
- UOPS_PORT_49: 4.14
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 5.6
- UOPS_PORT_5B>=2: 1.03
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 5 NOPs

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.33
- Reference cycles: 4.37
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 7.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.88
- UOPS_PORT_1: 2.87
- UOPS_PORT_6: 2.87
- UOPS_PORT_49: 3.68
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 5.57
- UOPS_PORT_5B>=2: 1.15
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 7.39
- Reference cycles: 4.35
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.78
- UOPS_PORT_1: 2.71
- UOPS_PORT_6: 3.05
- UOPS_PORT_49: 5.66
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 5.97
- UOPS_PORT_5B>=2: 1.19
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 7.39
- Reference cycles: 4.35
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.83
- UOPS_PORT_1: 2.66
- UOPS_PORT_6: 2.99
- UOPS_PORT_49: 5.66
- UOPS_PORT_78: 1.0
- UOPS_PORT_5B: 5.95
- UOPS_PORT_5B>=2: 1.22
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	47 01 44 2e 04       	add    DWORD PTR [r14+r13*1+0x4],r8d
   9:	47 01 44 2e 08       	add    DWORD PTR [r14+r13*1+0x8],r8d
   e:	47 01 44 2e 0c       	add    DWORD PTR [r14+r13*1+0xc],r8d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 8.32
- Reference cycles: 4.93
- UOPS_EXECUTED.THREAD: 15.99
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 7.94
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.79
- UOPS_PORT_1: 3.56
- UOPS_PORT_6: 4.02
- UOPS_PORT_49: 4.87
- UOPS_PORT_78: 4.0
- UOPS_PORT_5B: 7.71
- UOPS_PORT_5B>=2: 1.7
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.99

With loop_count=1000 and unroll_count=2

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	47 01 44 2e 04       	add    DWORD PTR [r14+r13*1+0x4],r8d
   9:	47 01 44 2e 08       	add    DWORD PTR [r14+r13*1+0x8],r8d
   e:	47 01 44 2e 0c       	add    DWORD PTR [r14+r13*1+0xc],r8d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 8.05
- Reference cycles: 4.74
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.36
- UOPS_PORT_1: 3.42
- UOPS_PORT_6: 3.95
- UOPS_PORT_49: 5.73
- UOPS_PORT_78: 4.0
- UOPS_PORT_5B: 7.01
- UOPS_PORT_5B>=2: 1.42
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	47 01 44 2e 04       	add    DWORD PTR [r14+r13*1+0x4],r8d
   9:	47 01 44 2e 08       	add    DWORD PTR [r14+r13*1+0x8],r8d
   e:	47 01 44 2e 0c       	add    DWORD PTR [r14+r13*1+0xc],r8d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 8.31
- Reference cycles: 4.88
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 0.07
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.58
- UOPS_PORT_1: 3.63
- UOPS_PORT_6: 3.83
- UOPS_PORT_49: 4.73
- UOPS_PORT_78: 4.0
- UOPS_PORT_5B: 7.66
- UOPS_PORT_5B>=2: 1.59
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	47 01 44 2e 04       	add    DWORD PTR [r14+r13*1+0x4],r8d
   9:	47 01 44 2e 08       	add    DWORD PTR [r14+r13*1+0x8],r8d
   e:	47 01 44 2e 0c       	add    DWORD PTR [r14+r13*1+0xc],r8d
  13:	47 01 44 2e 10       	add    DWORD PTR [r14+r13*1+0x10],r8d
  18:	47 01 44 2e 14       	add    DWORD PTR [r14+r13*1+0x14],r8d
  1d:	47 01 44 2e 18       	add    DWORD PTR [r14+r13*1+0x18],r8d
  22:	47 01 44 2e 1c       	add    DWORD PTR [r14+r13*1+0x1c],r8d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 4.4
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.59
- UOPS_PORT_1: 1.59
- UOPS_PORT_6: 1.61
- UOPS_PORT_49: 8.0
- UOPS_PORT_78: 8.0
- UOPS_PORT_5B: 3.21
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.99

With loop_count=1000 and unroll_count=1

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	47 01 44 2e 04       	add    DWORD PTR [r14+r13*1+0x4],r8d
   9:	47 01 44 2e 08       	add    DWORD PTR [r14+r13*1+0x8],r8d
   e:	47 01 44 2e 0c       	add    DWORD PTR [r14+r13*1+0xc],r8d
  13:	47 01 44 2e 10       	add    DWORD PTR [r14+r13*1+0x10],r8d
  18:	47 01 44 2e 14       	add    DWORD PTR [r14+r13*1+0x14],r8d
  1d:	47 01 44 2e 18       	add    DWORD PTR [r14+r13*1+0x18],r8d
  22:	47 01 44 2e 1c       	add    DWORD PTR [r14+r13*1+0x1c],r8d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.09
- Reference cycles: 4.73
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.64
- UOPS_PORT_1: 3.71
- UOPS_PORT_6: 4.47
- UOPS_PORT_49: 8.83
- UOPS_PORT_78: 8.0
- UOPS_PORT_5B: 7.82
- UOPS_PORT_5B>=2: 1.82
- UOPS_PORT_23A: 8.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	47 01 44 2e 04       	add    DWORD PTR [r14+r13*1+0x4],r8d
   9:	47 01 44 2e 08       	add    DWORD PTR [r14+r13*1+0x8],r8d
   e:	47 01 44 2e 0c       	add    DWORD PTR [r14+r13*1+0xc],r8d
  13:	47 01 44 2e 10       	add    DWORD PTR [r14+r13*1+0x10],r8d
  18:	47 01 44 2e 14       	add    DWORD PTR [r14+r13*1+0x14],r8d
  1d:	47 01 44 2e 18       	add    DWORD PTR [r14+r13*1+0x18],r8d
  22:	47 01 44 2e 1c       	add    DWORD PTR [r14+r13*1+0x1c],r8d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 7.58
- Reference cycles: 4.43
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.18
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.26
- UOPS_PORT_1: 3.32
- UOPS_PORT_6: 3.51
- UOPS_PORT_49: 8.59
- UOPS_PORT_78: 8.0
- UOPS_PORT_5B: 7.05
- UOPS_PORT_5B>=2: 1.55
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	47 01 44 2e 04       	add    DWORD PTR [r14+r13*1+0x4],r8d
   9:	47 01 44 2e 08       	add    DWORD PTR [r14+r13*1+0x8],r8d
   e:	47 01 44 2e 0c       	add    DWORD PTR [r14+r13*1+0xc],r8d
  13:	47 01 44 2e 10       	add    DWORD PTR [r14+r13*1+0x10],r8d
  18:	47 01 44 2e 14       	add    DWORD PTR [r14+r13*1+0x14],r8d
  1d:	47 01 44 2e 18       	add    DWORD PTR [r14+r13*1+0x18],r8d
  22:	47 01 44 2e 1c       	add    DWORD PTR [r14+r13*1+0x1c],r8d
  27:	47 01 44 2e 20       	add    DWORD PTR [r14+r13*1+0x20],r8d
  2c:	47 01 44 2e 24       	add    DWORD PTR [r14+r13*1+0x24],r8d
  31:	47 01 44 2e 28       	add    DWORD PTR [r14+r13*1+0x28],r8d
  36:	47 01 44 2e 2c       	add    DWORD PTR [r14+r13*1+0x2c],r8d
  3b:	47 01 44 2e 30       	add    DWORD PTR [r14+r13*1+0x30],r8d
  40:	47 01 44 2e 34       	add    DWORD PTR [r14+r13*1+0x34],r8d
  45:	47 01 44 2e 38       	add    DWORD PTR [r14+r13*1+0x38],r8d
  4a:	47 01 44 2e 3c       	add    DWORD PTR [r14+r13*1+0x3c],r8d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 9.6
- UOPS_EXECUTED.THREAD: 64.0
- RETIRE_SLOTS: 48.0
- UOPS_MITE: 32.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.21
- UOPS_PORT_1: 3.21
- UOPS_PORT_6: 3.19
- UOPS_PORT_49: 16.0
- UOPS_PORT_78: 16.0
- UOPS_PORT_5B: 6.39
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.01

With loop_count=1000 and unroll_count=1

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	47 01 44 2e 04       	add    DWORD PTR [r14+r13*1+0x4],r8d
   9:	47 01 44 2e 08       	add    DWORD PTR [r14+r13*1+0x8],r8d
   e:	47 01 44 2e 0c       	add    DWORD PTR [r14+r13*1+0xc],r8d
  13:	47 01 44 2e 10       	add    DWORD PTR [r14+r13*1+0x10],r8d
  18:	47 01 44 2e 14       	add    DWORD PTR [r14+r13*1+0x14],r8d
  1d:	47 01 44 2e 18       	add    DWORD PTR [r14+r13*1+0x18],r8d
  22:	47 01 44 2e 1c       	add    DWORD PTR [r14+r13*1+0x1c],r8d
  27:	47 01 44 2e 20       	add    DWORD PTR [r14+r13*1+0x20],r8d
  2c:	47 01 44 2e 24       	add    DWORD PTR [r14+r13*1+0x24],r8d
  31:	47 01 44 2e 28       	add    DWORD PTR [r14+r13*1+0x28],r8d
  36:	47 01 44 2e 2c       	add    DWORD PTR [r14+r13*1+0x2c],r8d
  3b:	47 01 44 2e 30       	add    DWORD PTR [r14+r13*1+0x30],r8d
  40:	47 01 44 2e 34       	add    DWORD PTR [r14+r13*1+0x34],r8d
  45:	47 01 44 2e 38       	add    DWORD PTR [r14+r13*1+0x38],r8d
  4a:	47 01 44 2e 3c       	add    DWORD PTR [r14+r13*1+0x3c],r8d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 9.38
- Reference cycles: 5.49
- UOPS_EXECUTED.THREAD: 65.02
- RETIRE_SLOTS: 49.0
- UOPS_MITE: 0.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.98
- UOPS_PORT_1: 4.07
- UOPS_PORT_6: 4.81
- UOPS_PORT_49: 16.01
- UOPS_PORT_78: 16.01
- UOPS_PORT_5B: 8.48
- UOPS_PORT_5B>=2: 1.88
- UOPS_PORT_23A: 16.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With loop_count=100 and unroll_count=10

Code:

   0:	47 01 04 2e          	add    DWORD PTR [r14+r13*1],r8d
   4:	47 01 44 2e 04       	add    DWORD PTR [r14+r13*1+0x4],r8d
   9:	47 01 44 2e 08       	add    DWORD PTR [r14+r13*1+0x8],r8d
   e:	47 01 44 2e 0c       	add    DWORD PTR [r14+r13*1+0xc],r8d
  13:	47 01 44 2e 10       	add    DWORD PTR [r14+r13*1+0x10],r8d
  18:	47 01 44 2e 14       	add    DWORD PTR [r14+r13*1+0x14],r8d
  1d:	47 01 44 2e 18       	add    DWORD PTR [r14+r13*1+0x18],r8d
  22:	47 01 44 2e 1c       	add    DWORD PTR [r14+r13*1+0x1c],r8d
  27:	47 01 44 2e 20       	add    DWORD PTR [r14+r13*1+0x20],r8d
  2c:	47 01 44 2e 24       	add    DWORD PTR [r14+r13*1+0x24],r8d
  31:	47 01 44 2e 28       	add    DWORD PTR [r14+r13*1+0x28],r8d
  36:	47 01 44 2e 2c       	add    DWORD PTR [r14+r13*1+0x2c],r8d
  3b:	47 01 44 2e 30       	add    DWORD PTR [r14+r13*1+0x30],r8d
  40:	47 01 44 2e 34       	add    DWORD PTR [r14+r13*1+0x34],r8d
  45:	47 01 44 2e 38       	add    DWORD PTR [r14+r13*1+0x38],r8d
  4a:	47 01 44 2e 3c       	add    DWORD PTR [r14+r13*1+0x3c],r8d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 9.44
- Reference cycles: 5.55
- UOPS_EXECUTED.THREAD: 64.1
- RETIRE_SLOTS: 48.1
- UOPS_MITE: 0.34
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.33
- UOPS_PORT_1: 3.42
- UOPS_PORT_6: 3.79
- UOPS_PORT_49: 16.0
- UOPS_PORT_78: 16.0
- UOPS_PORT_5B: 8.48
- UOPS_PORT_5B>=2: 1.85
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.17

ADD (M32, R32) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With unroll_count=500, no inner loop, and 5 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With unroll_count=500, no inner loop, and 5 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10