ADD (M8, R8h)

With unroll_count=500 and no inner loop

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 6.02
- Reference cycles: 5.38
- UOPS_EXECUTED.CORE: 4.0
- RETIRE_SLOTS: 2.0
- UOPS_MITE: 2.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.72
- UOPS_PORT_1: 1.99
- UOPS_PORT_2: 0.96
- UOPS_PORT_3: 0.94
- UOPS_PORT_4: 1.7
- UOPS_PORT_5: 2.02
- UOPS_PORT_6: 2.08
- UOPS_PORT_7: 0.1
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	90                   	nop

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 7.44
- Reference cycles: 6.62
- UOPS_EXECUTED.CORE: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.8
- UOPS_PORT_1: 1.81
- UOPS_PORT_2: 0.74
- UOPS_PORT_3: 0.8
- UOPS_PORT_4: 3.4
- UOPS_PORT_5: 1.89
- UOPS_PORT_6: 1.97
- UOPS_PORT_7: 0.46
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	90                   	nop
   3:	90                   	nop

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 7.4
- Reference cycles: 6.59
- UOPS_EXECUTED.CORE: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.92
- UOPS_PORT_1: 1.96
- UOPS_PORT_2: 0.93
- UOPS_PORT_3: 1.05
- UOPS_PORT_4: 1.54
- UOPS_PORT_5: 1.96
- UOPS_PORT_6: 1.99
- UOPS_PORT_7: 0.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	90                   	nop
   3:	90                   	nop
   4:	90                   	nop

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.0
- Reference cycles: 5.33
- UOPS_EXECUTED.CORE: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.59
- UOPS_PORT_1: 1.65
- UOPS_PORT_2: 0.69
- UOPS_PORT_3: 0.75
- UOPS_PORT_4: 5.88
- UOPS_PORT_5: 1.75
- UOPS_PORT_6: 1.78
- UOPS_PORT_7: 0.53
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 6.0
- Reference cycles: 5.49
- UOPS_EXECUTED.CORE: 4.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 2.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.56
- UOPS_PORT_1: 1.62
- UOPS_PORT_2: 0.78
- UOPS_PORT_3: 0.88
- UOPS_PORT_4: 5.21
- UOPS_PORT_5: 1.66
- UOPS_PORT_6: 1.75
- UOPS_PORT_7: 0.35
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (long NOPs)

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
   9:	0f 1f 84 00 00 00 00 
  10:	00

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 6.16
- Reference cycles: 5.63
- UOPS_EXECUTED.CORE: 4.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.71
- UOPS_PORT_1: 1.77
- UOPS_PORT_2: 0.72
- UOPS_PORT_3: 0.8
- UOPS_PORT_4: 5.1
- UOPS_PORT_5: 1.72
- UOPS_PORT_6: 1.86
- UOPS_PORT_7: 0.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 6.01
- Reference cycles: 5.35
- UOPS_EXECUTED.CORE: 4.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 2.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.56
- UOPS_PORT_1: 1.65
- UOPS_PORT_2: 0.77
- UOPS_PORT_3: 0.91
- UOPS_PORT_4: 5.14
- UOPS_PORT_5: 1.69
- UOPS_PORT_6: 1.61
- UOPS_PORT_7: 0.32
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (long NOPs)

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
   9:	0f 1f 84 00 00 00 00 
  10:	00

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 6.23
- Reference cycles: 5.54
- UOPS_EXECUTED.CORE: 4.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.7
- UOPS_PORT_1: 1.73
- UOPS_PORT_2: 0.7
- UOPS_PORT_3: 0.8
- UOPS_PORT_4: 5.65
- UOPS_PORT_5: 1.72
- UOPS_PORT_6: 1.79
- UOPS_PORT_7: 0.49
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	00 7f 01             	add    BYTE PTR [rdi+0x1],bh
   5:	00 7f 02             	add    BYTE PTR [rdi+0x2],bh
   8:	00 7f 03             	add    BYTE PTR [rdi+0x3],bh

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.05
- Reference cycles: 5.41
- UOPS_EXECUTED.CORE: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.23
- UOPS_PORT_1: 2.28
- UOPS_PORT_2: 3.03
- UOPS_PORT_3: 2.86
- UOPS_PORT_4: 5.91
- UOPS_PORT_5: 2.4
- UOPS_PORT_6: 2.59
- UOPS_PORT_7: 2.11
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	00 7f 01             	add    BYTE PTR [rdi+0x1],bh
   5:	00 7f 02             	add    BYTE PTR [rdi+0x2],bh
   8:	00 7f 03             	add    BYTE PTR [rdi+0x3],bh

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 6.05
- Reference cycles: 5.38
- UOPS_EXECUTED.CORE: 16.5
- RETIRE_SLOTS: 8.5
- UOPS_MITE: 0.56
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.42
- UOPS_PORT_1: 2.44
- UOPS_PORT_2: 2.88
- UOPS_PORT_3: 3.1
- UOPS_PORT_4: 5.99
- UOPS_PORT_5: 2.5
- UOPS_PORT_6: 2.89
- UOPS_PORT_7: 2.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.26

With loop_count=1000, unroll_count=2, and padding (long NOPs)

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	00 7f 01             	add    BYTE PTR [rdi+0x1],bh
   5:	00 7f 02             	add    BYTE PTR [rdi+0x2],bh
   8:	00 7f 03             	add    BYTE PTR [rdi+0x3],bh
   b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  12:	0f 1f 84 00 00 00 00 
  19:	00

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.21
- Reference cycles: 5.52
- UOPS_EXECUTED.CORE: 16.5
- RETIRE_SLOTS: 9.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.37
- UOPS_PORT_1: 2.47
- UOPS_PORT_2: 2.97
- UOPS_PORT_3: 3.05
- UOPS_PORT_4: 5.93
- UOPS_PORT_5: 2.54
- UOPS_PORT_6: 2.84
- UOPS_PORT_7: 1.99
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	00 7f 01             	add    BYTE PTR [rdi+0x1],bh
   5:	00 7f 02             	add    BYTE PTR [rdi+0x2],bh
   8:	00 7f 03             	add    BYTE PTR [rdi+0x3],bh

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 6.02
- Reference cycles: 5.35
- UOPS_EXECUTED.CORE: 16.05
- RETIRE_SLOTS: 8.05
- UOPS_MITE: 8.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.33
- UOPS_PORT_1: 2.4
- UOPS_PORT_2: 2.96
- UOPS_PORT_3: 2.9
- UOPS_PORT_4: 5.97
- UOPS_PORT_5: 2.45
- UOPS_PORT_6: 2.44
- UOPS_PORT_7: 2.14
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.01

With loop_count=100, unroll_count=20, and padding (long NOPs)

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	00 7f 01             	add    BYTE PTR [rdi+0x1],bh
   5:	00 7f 02             	add    BYTE PTR [rdi+0x2],bh
   8:	00 7f 03             	add    BYTE PTR [rdi+0x3],bh
   b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  12:	0f 1f 84 00 00 00 00 
  19:	00

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 5.1
- Core cycles: 6.07
- Reference cycles: 5.4
- UOPS_EXECUTED.CORE: 16.05
- RETIRE_SLOTS: 9.05
- UOPS_MITE: 0.09
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.35
- UOPS_PORT_1: 2.39
- UOPS_PORT_2: 2.9
- UOPS_PORT_3: 2.95
- UOPS_PORT_4: 5.93
- UOPS_PORT_5: 2.46
- UOPS_PORT_6: 2.59
- UOPS_PORT_7: 2.15
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	00 7f 01             	add    BYTE PTR [rdi+0x1],bh
   5:	00 7f 02             	add    BYTE PTR [rdi+0x2],bh
   8:	00 7f 03             	add    BYTE PTR [rdi+0x3],bh
   b:	00 7f 04             	add    BYTE PTR [rdi+0x4],bh
   e:	00 7f 05             	add    BYTE PTR [rdi+0x5],bh
  11:	00 7f 06             	add    BYTE PTR [rdi+0x6],bh
  14:	00 7f 07             	add    BYTE PTR [rdi+0x7],bh

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.62
- Reference cycles: 7.79
- UOPS_EXECUTED.CORE: 32.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.56
- UOPS_PORT_1: 3.84
- UOPS_PORT_2: 5.71
- UOPS_PORT_3: 6.19
- UOPS_PORT_4: 8.02
- UOPS_PORT_5: 3.84
- UOPS_PORT_6: 3.93
- UOPS_PORT_7: 4.08
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	00 7f 01             	add    BYTE PTR [rdi+0x1],bh
   5:	00 7f 02             	add    BYTE PTR [rdi+0x2],bh
   8:	00 7f 03             	add    BYTE PTR [rdi+0x3],bh
   b:	00 7f 04             	add    BYTE PTR [rdi+0x4],bh
   e:	00 7f 05             	add    BYTE PTR [rdi+0x5],bh
  11:	00 7f 06             	add    BYTE PTR [rdi+0x6],bh
  14:	00 7f 07             	add    BYTE PTR [rdi+0x7],bh

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 9.04
- Reference cycles: 8.03
- UOPS_EXECUTED.CORE: 33.01
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.84
- UOPS_PORT_1: 3.92
- UOPS_PORT_2: 5.68
- UOPS_PORT_3: 6.05
- UOPS_PORT_4: 8.01
- UOPS_PORT_5: 4.02
- UOPS_PORT_6: 4.69
- UOPS_PORT_7: 4.28
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	00 7f 01             	add    BYTE PTR [rdi+0x1],bh
   5:	00 7f 02             	add    BYTE PTR [rdi+0x2],bh
   8:	00 7f 03             	add    BYTE PTR [rdi+0x3],bh
   b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  12:	0f 1f 84 00 00 00 00 
  19:	00 
  1a:	00 7f 04             	add    BYTE PTR [rdi+0x4],bh
  1d:	00 7f 05             	add    BYTE PTR [rdi+0x5],bh
  20:	00 7f 06             	add    BYTE PTR [rdi+0x6],bh
  23:	00 7f 07             	add    BYTE PTR [rdi+0x7],bh
  26:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  2d:	0f 1f 84 00 00 00 00 
  34:	00

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 8.99
- Reference cycles: 8.0
- UOPS_EXECUTED.CORE: 33.01
- RETIRE_SLOTS: 19.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.9
- UOPS_PORT_1: 3.91
- UOPS_PORT_2: 5.78
- UOPS_PORT_3: 5.76
- UOPS_PORT_4: 8.01
- UOPS_PORT_5: 4.05
- UOPS_PORT_6: 4.71
- UOPS_PORT_7: 4.43
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	00 7f 01             	add    BYTE PTR [rdi+0x1],bh
   5:	00 7f 02             	add    BYTE PTR [rdi+0x2],bh
   8:	00 7f 03             	add    BYTE PTR [rdi+0x3],bh
   b:	00 7f 04             	add    BYTE PTR [rdi+0x4],bh
   e:	00 7f 05             	add    BYTE PTR [rdi+0x5],bh
  11:	00 7f 06             	add    BYTE PTR [rdi+0x6],bh
  14:	00 7f 07             	add    BYTE PTR [rdi+0x7],bh

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.72
- Reference cycles: 7.98
- UOPS_EXECUTED.CORE: 32.11
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 16.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.78
- UOPS_PORT_1: 3.84
- UOPS_PORT_2: 5.74
- UOPS_PORT_3: 5.87
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 3.88
- UOPS_PORT_6: 3.74
- UOPS_PORT_7: 4.39
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.03

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	00 7f 01             	add    BYTE PTR [rdi+0x1],bh
   5:	00 7f 02             	add    BYTE PTR [rdi+0x2],bh
   8:	00 7f 03             	add    BYTE PTR [rdi+0x3],bh
   b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  12:	0f 1f 84 00 00 00 00 
  19:	00 
  1a:	00 7f 04             	add    BYTE PTR [rdi+0x4],bh
  1d:	00 7f 05             	add    BYTE PTR [rdi+0x5],bh
  20:	00 7f 06             	add    BYTE PTR [rdi+0x6],bh
  23:	00 7f 07             	add    BYTE PTR [rdi+0x7],bh
  26:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  2d:	0f 1f 84 00 00 00 00 
  34:	00

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 10.2
- Core cycles: 8.78
- Reference cycles: 7.8
- UOPS_EXECUTED.CORE: 32.11
- RETIRE_SLOTS: 18.1
- UOPS_MITE: 0.18
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.65
- UOPS_PORT_1: 3.8
- UOPS_PORT_2: 5.57
- UOPS_PORT_3: 5.96
- UOPS_PORT_4: 8.01
- UOPS_PORT_5: 3.85
- UOPS_PORT_6: 4.02
- UOPS_PORT_7: 4.47
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	00 7f 01             	add    BYTE PTR [rdi+0x1],bh
   5:	00 7f 02             	add    BYTE PTR [rdi+0x2],bh
   8:	00 7f 03             	add    BYTE PTR [rdi+0x3],bh
   b:	00 7f 04             	add    BYTE PTR [rdi+0x4],bh
   e:	00 7f 05             	add    BYTE PTR [rdi+0x5],bh
  11:	00 7f 06             	add    BYTE PTR [rdi+0x6],bh
  14:	00 7f 07             	add    BYTE PTR [rdi+0x7],bh
  17:	00 7f 08             	add    BYTE PTR [rdi+0x8],bh
  1a:	00 7f 09             	add    BYTE PTR [rdi+0x9],bh
  1d:	00 7f 0a             	add    BYTE PTR [rdi+0xa],bh
  20:	00 7f 0b             	add    BYTE PTR [rdi+0xb],bh
  23:	00 7f 0c             	add    BYTE PTR [rdi+0xc],bh
  26:	00 7f 0d             	add    BYTE PTR [rdi+0xd],bh
  29:	00 7f 0e             	add    BYTE PTR [rdi+0xe],bh
  2c:	00 7f 0f             	add    BYTE PTR [rdi+0xf],bh

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 17.43
- Reference cycles: 15.63
- UOPS_EXECUTED.CORE: 64.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.63
- UOPS_PORT_1: 5.9
- UOPS_PORT_2: 11.6
- UOPS_PORT_3: 11.7
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 7.1
- UOPS_PORT_6: 7.4
- UOPS_PORT_7: 9.18
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.02

With loop_count=1000 and unroll_count=1

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	00 7f 01             	add    BYTE PTR [rdi+0x1],bh
   5:	00 7f 02             	add    BYTE PTR [rdi+0x2],bh
   8:	00 7f 03             	add    BYTE PTR [rdi+0x3],bh
   b:	00 7f 04             	add    BYTE PTR [rdi+0x4],bh
   e:	00 7f 05             	add    BYTE PTR [rdi+0x5],bh
  11:	00 7f 06             	add    BYTE PTR [rdi+0x6],bh
  14:	00 7f 07             	add    BYTE PTR [rdi+0x7],bh
  17:	00 7f 08             	add    BYTE PTR [rdi+0x8],bh
  1a:	00 7f 09             	add    BYTE PTR [rdi+0x9],bh
  1d:	00 7f 0a             	add    BYTE PTR [rdi+0xa],bh
  20:	00 7f 0b             	add    BYTE PTR [rdi+0xb],bh
  23:	00 7f 0c             	add    BYTE PTR [rdi+0xc],bh
  26:	00 7f 0d             	add    BYTE PTR [rdi+0xd],bh
  29:	00 7f 0e             	add    BYTE PTR [rdi+0xe],bh
  2c:	00 7f 0f             	add    BYTE PTR [rdi+0xf],bh

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 17.81
- Reference cycles: 15.83
- UOPS_EXECUTED.CORE: 65.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 33.05
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.73
- UOPS_PORT_1: 6.84
- UOPS_PORT_2: 11.27
- UOPS_PORT_3: 11.94
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 7.1
- UOPS_PORT_6: 7.73
- UOPS_PORT_7: 8.8
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	00 7f 01             	add    BYTE PTR [rdi+0x1],bh
   5:	00 7f 02             	add    BYTE PTR [rdi+0x2],bh
   8:	00 7f 03             	add    BYTE PTR [rdi+0x3],bh
   b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  12:	0f 1f 84 00 00 00 00 
  19:	00 
  1a:	00 7f 04             	add    BYTE PTR [rdi+0x4],bh
  1d:	00 7f 05             	add    BYTE PTR [rdi+0x5],bh
  20:	00 7f 06             	add    BYTE PTR [rdi+0x6],bh
  23:	00 7f 07             	add    BYTE PTR [rdi+0x7],bh
  26:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  2d:	0f 1f 84 00 00 00 00 
  34:	00 
  35:	00 7f 08             	add    BYTE PTR [rdi+0x8],bh
  38:	00 7f 09             	add    BYTE PTR [rdi+0x9],bh
  3b:	00 7f 0a             	add    BYTE PTR [rdi+0xa],bh
  3e:	00 7f 0b             	add    BYTE PTR [rdi+0xb],bh
  41:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  48:	0f 1f 84 00 00 00 00 
  4f:	00 
  50:	00 7f 0c             	add    BYTE PTR [rdi+0xc],bh
  53:	00 7f 0d             	add    BYTE PTR [rdi+0xd],bh
  56:	00 7f 0e             	add    BYTE PTR [rdi+0xe],bh
  59:	00 7f 0f             	add    BYTE PTR [rdi+0xf],bh
  5c:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  63:	0f 1f 84 00 00 00 00 
  6a:	00

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 22.0
- Core cycles: 17.89
- Reference cycles: 15.9
- UOPS_EXECUTED.CORE: 65.01
- RETIRE_SLOTS: 37.0
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.83
- UOPS_PORT_1: 7.01
- UOPS_PORT_2: 11.5
- UOPS_PORT_3: 11.51
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 7.22
- UOPS_PORT_6: 7.98
- UOPS_PORT_7: 9.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	00 7f 01             	add    BYTE PTR [rdi+0x1],bh
   5:	00 7f 02             	add    BYTE PTR [rdi+0x2],bh
   8:	00 7f 03             	add    BYTE PTR [rdi+0x3],bh
   b:	00 7f 04             	add    BYTE PTR [rdi+0x4],bh
   e:	00 7f 05             	add    BYTE PTR [rdi+0x5],bh
  11:	00 7f 06             	add    BYTE PTR [rdi+0x6],bh
  14:	00 7f 07             	add    BYTE PTR [rdi+0x7],bh
  17:	00 7f 08             	add    BYTE PTR [rdi+0x8],bh
  1a:	00 7f 09             	add    BYTE PTR [rdi+0x9],bh
  1d:	00 7f 0a             	add    BYTE PTR [rdi+0xa],bh
  20:	00 7f 0b             	add    BYTE PTR [rdi+0xb],bh
  23:	00 7f 0c             	add    BYTE PTR [rdi+0xc],bh
  26:	00 7f 0d             	add    BYTE PTR [rdi+0xd],bh
  29:	00 7f 0e             	add    BYTE PTR [rdi+0xe],bh
  2c:	00 7f 0f             	add    BYTE PTR [rdi+0xf],bh

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 17.52
- Reference cycles: 15.58
- UOPS_EXECUTED.CORE: 64.11
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 32.15
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.39
- UOPS_PORT_1: 6.68
- UOPS_PORT_2: 11.35
- UOPS_PORT_3: 11.55
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 7.19
- UOPS_PORT_6: 6.96
- UOPS_PORT_7: 9.16
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.03

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	00 3f                	add    BYTE PTR [rdi],bh
   2:	00 7f 01             	add    BYTE PTR [rdi+0x1],bh
   5:	00 7f 02             	add    BYTE PTR [rdi+0x2],bh
   8:	00 7f 03             	add    BYTE PTR [rdi+0x3],bh
   b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  12:	0f 1f 84 00 00 00 00 
  19:	00 
  1a:	00 7f 04             	add    BYTE PTR [rdi+0x4],bh
  1d:	00 7f 05             	add    BYTE PTR [rdi+0x5],bh
  20:	00 7f 06             	add    BYTE PTR [rdi+0x6],bh
  23:	00 7f 07             	add    BYTE PTR [rdi+0x7],bh
  26:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  2d:	0f 1f 84 00 00 00 00 
  34:	00 
  35:	00 7f 08             	add    BYTE PTR [rdi+0x8],bh
  38:	00 7f 09             	add    BYTE PTR [rdi+0x9],bh
  3b:	00 7f 0a             	add    BYTE PTR [rdi+0xa],bh
  3e:	00 7f 0b             	add    BYTE PTR [rdi+0xb],bh
  41:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  48:	0f 1f 84 00 00 00 00 
  4f:	00 
  50:	00 7f 0c             	add    BYTE PTR [rdi+0xc],bh
  53:	00 7f 0d             	add    BYTE PTR [rdi+0xd],bh
  56:	00 7f 0e             	add    BYTE PTR [rdi+0xe],bh
  59:	00 7f 0f             	add    BYTE PTR [rdi+0xf],bh
  5c:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  63:	0f 1f 84 00 00 00 00 
  6a:	00

Init:
```
MOV BH, 0
```
Show nanoBench command
Results:
- Instructions retired: 20.2
- Core cycles: 17.68
- Reference cycles: 15.73
- UOPS_EXECUTED.CORE: 64.11
- RETIRE_SLOTS: 36.1
- UOPS_MITE: 0.36
- UOPS_MS: 0.0
- UOPS_PORT_0: 6.67
- UOPS_PORT_1: 6.9
- UOPS_PORT_2: 11.08
- UOPS_PORT_3: 11.98
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 7.09
- UOPS_PORT_6: 7.31
- UOPS_PORT_7: 9.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 6.01
- Reference cycles: 5.35
- UOPS_EXECUTED.CORE: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 2.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.65
- UOPS_PORT_1: 1.56
- UOPS_PORT_2: 0.93
- UOPS_PORT_3: 1.07
- UOPS_PORT_4: 5.9
- UOPS_PORT_5: 1.97
- UOPS_PORT_6: 1.41
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	90                   	nop

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 5.34
- UOPS_EXECUTED.CORE: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.79
- UOPS_PORT_1: 2.0
- UOPS_PORT_2: 1.41
- UOPS_PORT_3: 0.58
- UOPS_PORT_4: 5.82
- UOPS_PORT_5: 1.76
- UOPS_PORT_6: 1.83
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	90                   	nop
   4:	90                   	nop

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 7.48
- Reference cycles: 6.63
- UOPS_EXECUTED.CORE: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.9
- UOPS_PORT_1: 1.88
- UOPS_PORT_2: 0.89
- UOPS_PORT_3: 1.1
- UOPS_PORT_4: 1.59
- UOPS_PORT_5: 2.01
- UOPS_PORT_6: 2.15
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	90                   	nop
   4:	90                   	nop
   5:	90                   	nop

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.01
- Reference cycles: 5.34
- UOPS_EXECUTED.CORE: 4.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.61
- UOPS_PORT_1: 1.61
- UOPS_PORT_2: 0.95
- UOPS_PORT_3: 1.05
- UOPS_PORT_4: 5.32
- UOPS_PORT_5: 1.32
- UOPS_PORT_6: 1.66
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 6.0
- Reference cycles: 5.33
- UOPS_EXECUTED.CORE: 4.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 2.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.67
- UOPS_PORT_1: 1.7
- UOPS_PORT_2: 0.9
- UOPS_PORT_3: 1.1
- UOPS_PORT_4: 5.47
- UOPS_PORT_5: 1.45
- UOPS_PORT_6: 1.74
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (long NOPs)

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
   a:	0f 1f 84 00 00 00 00 
  11:	00

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 6.0
- Reference cycles: 5.33
- UOPS_EXECUTED.CORE: 4.1
- RETIRE_SLOTS: 4.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.98
- UOPS_PORT_1: 2.01
- UOPS_PORT_2: 0.99
- UOPS_PORT_3: 1.01
- UOPS_PORT_4: 5.83
- UOPS_PORT_5: 1.75
- UOPS_PORT_6: 1.91
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 6.0
- Reference cycles: 5.33
- UOPS_EXECUTED.CORE: 4.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 2.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.92
- UOPS_PORT_1: 1.9
- UOPS_PORT_2: 0.95
- UOPS_PORT_3: 1.05
- UOPS_PORT_4: 5.98
- UOPS_PORT_5: 1.93
- UOPS_PORT_6: 1.21
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (long NOPs)

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
   a:	0f 1f 84 00 00 00 00 
  11:	00

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 7.0
- Reference cycles: 6.22
- UOPS_EXECUTED.CORE: 4.01
- RETIRE_SLOTS: 4.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.6
- UOPS_PORT_1: 1.65
- UOPS_PORT_2: 1.06
- UOPS_PORT_3: 0.94
- UOPS_PORT_4: 5.49
- UOPS_PORT_5: 1.63
- UOPS_PORT_6: 1.69
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	00 7c 37 01          	add    BYTE PTR [rdi+rsi*1+0x1],bh
   7:	00 7c 37 02          	add    BYTE PTR [rdi+rsi*1+0x2],bh
   b:	00 7c 37 03          	add    BYTE PTR [rdi+rsi*1+0x3],bh

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 6.09
- Reference cycles: 5.44
- UOPS_EXECUTED.CORE: 16.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.33
- UOPS_PORT_1: 2.29
- UOPS_PORT_2: 3.94
- UOPS_PORT_3: 4.06
- UOPS_PORT_4: 5.08
- UOPS_PORT_5: 2.13
- UOPS_PORT_6: 2.15
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	00 7c 37 01          	add    BYTE PTR [rdi+rsi*1+0x1],bh
   7:	00 7c 37 02          	add    BYTE PTR [rdi+rsi*1+0x2],bh
   b:	00 7c 37 03          	add    BYTE PTR [rdi+rsi*1+0x3],bh

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 7.65
- Reference cycles: 6.81
- UOPS_EXECUTED.CORE: 16.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.92
- UOPS_PORT_1: 2.98
- UOPS_PORT_2: 3.85
- UOPS_PORT_3: 4.15
- UOPS_PORT_4: 4.15
- UOPS_PORT_5: 2.79
- UOPS_PORT_6: 2.89
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=2, and padding (long NOPs)

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	00 7c 37 01          	add    BYTE PTR [rdi+rsi*1+0x1],bh
   7:	00 7c 37 02          	add    BYTE PTR [rdi+rsi*1+0x2],bh
   b:	00 7c 37 03          	add    BYTE PTR [rdi+rsi*1+0x3],bh
   f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  16:	0f 1f 84 00 00 00 00 
  1d:	00

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.68
- Reference cycles: 5.95
- UOPS_EXECUTED.CORE: 16.5
- RETIRE_SLOTS: 13.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.51
- UOPS_PORT_1: 2.54
- UOPS_PORT_2: 3.83
- UOPS_PORT_3: 4.17
- UOPS_PORT_4: 4.69
- UOPS_PORT_5: 2.41
- UOPS_PORT_6: 3.13
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	00 7c 37 01          	add    BYTE PTR [rdi+rsi*1+0x1],bh
   7:	00 7c 37 02          	add    BYTE PTR [rdi+rsi*1+0x2],bh
   b:	00 7c 37 03          	add    BYTE PTR [rdi+rsi*1+0x3],bh

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 7.61
- Reference cycles: 6.76
- UOPS_EXECUTED.CORE: 16.05
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.0
- UOPS_PORT_1: 3.07
- UOPS_PORT_2: 3.85
- UOPS_PORT_3: 4.15
- UOPS_PORT_4: 4.22
- UOPS_PORT_5: 2.78
- UOPS_PORT_6: 2.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With loop_count=100, unroll_count=20, and padding (long NOPs)

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	00 7c 37 01          	add    BYTE PTR [rdi+rsi*1+0x1],bh
   7:	00 7c 37 02          	add    BYTE PTR [rdi+rsi*1+0x2],bh
   b:	00 7c 37 03          	add    BYTE PTR [rdi+rsi*1+0x3],bh
   f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  16:	0f 1f 84 00 00 00 00 
  1d:	00

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 5.1
- Core cycles: 6.62
- Reference cycles: 5.89
- UOPS_EXECUTED.CORE: 16.05
- RETIRE_SLOTS: 13.05
- UOPS_MITE: 0.09
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.32
- UOPS_PORT_1: 2.41
- UOPS_PORT_2: 3.9
- UOPS_PORT_3: 4.11
- UOPS_PORT_4: 4.61
- UOPS_PORT_5: 2.22
- UOPS_PORT_6: 2.25
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	00 7c 37 01          	add    BYTE PTR [rdi+rsi*1+0x1],bh
   7:	00 7c 37 02          	add    BYTE PTR [rdi+rsi*1+0x2],bh
   b:	00 7c 37 03          	add    BYTE PTR [rdi+rsi*1+0x3],bh
   f:	00 7c 37 04          	add    BYTE PTR [rdi+rsi*1+0x4],bh
  13:	00 7c 37 05          	add    BYTE PTR [rdi+rsi*1+0x5],bh
  17:	00 7c 37 06          	add    BYTE PTR [rdi+rsi*1+0x6],bh
  1b:	00 7c 37 07          	add    BYTE PTR [rdi+rsi*1+0x7],bh

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.35
- Reference cycles: 7.47
- UOPS_EXECUTED.CORE: 32.0
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.49
- UOPS_PORT_1: 3.62
- UOPS_PORT_2: 7.94
- UOPS_PORT_3: 8.04
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 2.95
- UOPS_PORT_6: 2.86
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	00 7c 37 01          	add    BYTE PTR [rdi+rsi*1+0x1],bh
   7:	00 7c 37 02          	add    BYTE PTR [rdi+rsi*1+0x2],bh
   b:	00 7c 37 03          	add    BYTE PTR [rdi+rsi*1+0x3],bh
   f:	00 7c 37 04          	add    BYTE PTR [rdi+rsi*1+0x4],bh
  13:	00 7c 37 05          	add    BYTE PTR [rdi+rsi*1+0x5],bh
  17:	00 7c 37 06          	add    BYTE PTR [rdi+rsi*1+0x6],bh
  1b:	00 7c 37 07          	add    BYTE PTR [rdi+rsi*1+0x7],bh

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.14
- Reference cycles: 7.24
- UOPS_EXECUTED.CORE: 33.01
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.45
- UOPS_PORT_1: 2.69
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.9
- UOPS_PORT_6: 3.44
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	00 7c 37 01          	add    BYTE PTR [rdi+rsi*1+0x1],bh
   7:	00 7c 37 02          	add    BYTE PTR [rdi+rsi*1+0x2],bh
   b:	00 7c 37 03          	add    BYTE PTR [rdi+rsi*1+0x3],bh
   f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  16:	0f 1f 84 00 00 00 00 
  1d:	00 
  1e:	00 7c 37 04          	add    BYTE PTR [rdi+rsi*1+0x4],bh
  22:	00 7c 37 05          	add    BYTE PTR [rdi+rsi*1+0x5],bh
  26:	00 7c 37 06          	add    BYTE PTR [rdi+rsi*1+0x6],bh
  2a:	00 7c 37 07          	add    BYTE PTR [rdi+rsi*1+0x7],bh
  2e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  35:	0f 1f 84 00 00 00 00 
  3c:	00

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 8.78
- Reference cycles: 7.81
- UOPS_EXECUTED.CORE: 34.01
- RETIRE_SLOTS: 28.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.05
- UOPS_PORT_1: 4.22
- UOPS_PORT_2: 7.98
- UOPS_PORT_3: 8.04
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 4.19
- UOPS_PORT_6: 4.66
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	00 7c 37 01          	add    BYTE PTR [rdi+rsi*1+0x1],bh
   7:	00 7c 37 02          	add    BYTE PTR [rdi+rsi*1+0x2],bh
   b:	00 7c 37 03          	add    BYTE PTR [rdi+rsi*1+0x3],bh
   f:	00 7c 37 04          	add    BYTE PTR [rdi+rsi*1+0x4],bh
  13:	00 7c 37 05          	add    BYTE PTR [rdi+rsi*1+0x5],bh
  17:	00 7c 37 06          	add    BYTE PTR [rdi+rsi*1+0x6],bh
  1b:	00 7c 37 07          	add    BYTE PTR [rdi+rsi*1+0x7],bh

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.05
- Reference cycles: 7.16
- UOPS_EXECUTED.CORE: 32.11
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.06
- UOPS_PORT_1: 2.63
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 2.61
- UOPS_PORT_6: 0.87
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	00 7c 37 01          	add    BYTE PTR [rdi+rsi*1+0x1],bh
   7:	00 7c 37 02          	add    BYTE PTR [rdi+rsi*1+0x2],bh
   b:	00 7c 37 03          	add    BYTE PTR [rdi+rsi*1+0x3],bh
   f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  16:	0f 1f 84 00 00 00 00 
  1d:	00 
  1e:	00 7c 37 04          	add    BYTE PTR [rdi+rsi*1+0x4],bh
  22:	00 7c 37 05          	add    BYTE PTR [rdi+rsi*1+0x5],bh
  26:	00 7c 37 06          	add    BYTE PTR [rdi+rsi*1+0x6],bh
  2a:	00 7c 37 07          	add    BYTE PTR [rdi+rsi*1+0x7],bh
  2e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  35:	0f 1f 84 00 00 00 00 
  3c:	00

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 10.2
- Core cycles: 8.11
- Reference cycles: 7.22
- UOPS_EXECUTED.CORE: 32.11
- RETIRE_SLOTS: 26.1
- UOPS_MITE: 0.18
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.15
- UOPS_PORT_1: 2.47
- UOPS_PORT_2: 8.01
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.81
- UOPS_PORT_6: 2.73
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	00 7c 37 01          	add    BYTE PTR [rdi+rsi*1+0x1],bh
   7:	00 7c 37 02          	add    BYTE PTR [rdi+rsi*1+0x2],bh
   b:	00 7c 37 03          	add    BYTE PTR [rdi+rsi*1+0x3],bh
   f:	00 7c 37 04          	add    BYTE PTR [rdi+rsi*1+0x4],bh
  13:	00 7c 37 05          	add    BYTE PTR [rdi+rsi*1+0x5],bh
  17:	00 7c 37 06          	add    BYTE PTR [rdi+rsi*1+0x6],bh
  1b:	00 7c 37 07          	add    BYTE PTR [rdi+rsi*1+0x7],bh
  1f:	00 7c 37 08          	add    BYTE PTR [rdi+rsi*1+0x8],bh
  23:	00 7c 37 09          	add    BYTE PTR [rdi+rsi*1+0x9],bh
  27:	00 7c 37 0a          	add    BYTE PTR [rdi+rsi*1+0xa],bh
  2b:	00 7c 37 0b          	add    BYTE PTR [rdi+rsi*1+0xb],bh
  2f:	00 7c 37 0c          	add    BYTE PTR [rdi+rsi*1+0xc],bh
  33:	00 7c 37 0d          	add    BYTE PTR [rdi+rsi*1+0xd],bh
  37:	00 7c 37 0e          	add    BYTE PTR [rdi+rsi*1+0xe],bh
  3b:	00 7c 37 0f          	add    BYTE PTR [rdi+rsi*1+0xf],bh

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.27
- Reference cycles: 14.51
- UOPS_EXECUTED.CORE: 64.0
- RETIRE_SLOTS: 48.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.28
- UOPS_PORT_1: 5.23
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 16.0
- UOPS_PORT_4: 16.04
- UOPS_PORT_5: 5.34
- UOPS_PORT_6: 1.72
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	00 7c 37 01          	add    BYTE PTR [rdi+rsi*1+0x1],bh
   7:	00 7c 37 02          	add    BYTE PTR [rdi+rsi*1+0x2],bh
   b:	00 7c 37 03          	add    BYTE PTR [rdi+rsi*1+0x3],bh
   f:	00 7c 37 04          	add    BYTE PTR [rdi+rsi*1+0x4],bh
  13:	00 7c 37 05          	add    BYTE PTR [rdi+rsi*1+0x5],bh
  17:	00 7c 37 06          	add    BYTE PTR [rdi+rsi*1+0x6],bh
  1b:	00 7c 37 07          	add    BYTE PTR [rdi+rsi*1+0x7],bh
  1f:	00 7c 37 08          	add    BYTE PTR [rdi+rsi*1+0x8],bh
  23:	00 7c 37 09          	add    BYTE PTR [rdi+rsi*1+0x9],bh
  27:	00 7c 37 0a          	add    BYTE PTR [rdi+rsi*1+0xa],bh
  2b:	00 7c 37 0b          	add    BYTE PTR [rdi+rsi*1+0xb],bh
  2f:	00 7c 37 0c          	add    BYTE PTR [rdi+rsi*1+0xc],bh
  33:	00 7c 37 0d          	add    BYTE PTR [rdi+rsi*1+0xd],bh
  37:	00 7c 37 0e          	add    BYTE PTR [rdi+rsi*1+0xe],bh
  3b:	00 7c 37 0f          	add    BYTE PTR [rdi+rsi*1+0xf],bh

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.02
- Reference cycles: 14.25
- UOPS_EXECUTED.CORE: 65.01
- RETIRE_SLOTS: 49.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.34
- UOPS_PORT_1: 5.31
- UOPS_PORT_2: 16.01
- UOPS_PORT_3: 16.0
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 5.26
- UOPS_PORT_6: 2.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	00 7c 37 01          	add    BYTE PTR [rdi+rsi*1+0x1],bh
   7:	00 7c 37 02          	add    BYTE PTR [rdi+rsi*1+0x2],bh
   b:	00 7c 37 03          	add    BYTE PTR [rdi+rsi*1+0x3],bh
   f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  16:	0f 1f 84 00 00 00 00 
  1d:	00 
  1e:	00 7c 37 04          	add    BYTE PTR [rdi+rsi*1+0x4],bh
  22:	00 7c 37 05          	add    BYTE PTR [rdi+rsi*1+0x5],bh
  26:	00 7c 37 06          	add    BYTE PTR [rdi+rsi*1+0x6],bh
  2a:	00 7c 37 07          	add    BYTE PTR [rdi+rsi*1+0x7],bh
  2e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  35:	0f 1f 84 00 00 00 00 
  3c:	00 
  3d:	00 7c 37 08          	add    BYTE PTR [rdi+rsi*1+0x8],bh
  41:	00 7c 37 09          	add    BYTE PTR [rdi+rsi*1+0x9],bh
  45:	00 7c 37 0a          	add    BYTE PTR [rdi+rsi*1+0xa],bh
  49:	00 7c 37 0b          	add    BYTE PTR [rdi+rsi*1+0xb],bh
  4d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  54:	0f 1f 84 00 00 00 00 
  5b:	00 
  5c:	00 7c 37 0c          	add    BYTE PTR [rdi+rsi*1+0xc],bh
  60:	00 7c 37 0d          	add    BYTE PTR [rdi+rsi*1+0xd],bh
  64:	00 7c 37 0e          	add    BYTE PTR [rdi+rsi*1+0xe],bh
  68:	00 7c 37 0f          	add    BYTE PTR [rdi+rsi*1+0xf],bh
  6c:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  73:	0f 1f 84 00 00 00 00 
  7a:	00

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 22.0
- Core cycles: 16.18
- Reference cycles: 14.38
- UOPS_EXECUTED.CORE: 65.01
- RETIRE_SLOTS: 53.0
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.31
- UOPS_PORT_1: 4.67
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 16.01
- UOPS_PORT_4: 16.05
- UOPS_PORT_5: 2.75
- UOPS_PORT_6: 5.8
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	00 7c 37 01          	add    BYTE PTR [rdi+rsi*1+0x1],bh
   7:	00 7c 37 02          	add    BYTE PTR [rdi+rsi*1+0x2],bh
   b:	00 7c 37 03          	add    BYTE PTR [rdi+rsi*1+0x3],bh
   f:	00 7c 37 04          	add    BYTE PTR [rdi+rsi*1+0x4],bh
  13:	00 7c 37 05          	add    BYTE PTR [rdi+rsi*1+0x5],bh
  17:	00 7c 37 06          	add    BYTE PTR [rdi+rsi*1+0x6],bh
  1b:	00 7c 37 07          	add    BYTE PTR [rdi+rsi*1+0x7],bh
  1f:	00 7c 37 08          	add    BYTE PTR [rdi+rsi*1+0x8],bh
  23:	00 7c 37 09          	add    BYTE PTR [rdi+rsi*1+0x9],bh
  27:	00 7c 37 0a          	add    BYTE PTR [rdi+rsi*1+0xa],bh
  2b:	00 7c 37 0b          	add    BYTE PTR [rdi+rsi*1+0xb],bh
  2f:	00 7c 37 0c          	add    BYTE PTR [rdi+rsi*1+0xc],bh
  33:	00 7c 37 0d          	add    BYTE PTR [rdi+rsi*1+0xd],bh
  37:	00 7c 37 0e          	add    BYTE PTR [rdi+rsi*1+0xe],bh
  3b:	00 7c 37 0f          	add    BYTE PTR [rdi+rsi*1+0xf],bh

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.03
- Reference cycles: 14.26
- UOPS_EXECUTED.CORE: 64.11
- RETIRE_SLOTS: 48.1
- UOPS_MITE: 0.32
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.08
- UOPS_PORT_1: 5.2
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 16.0
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 1.47
- UOPS_PORT_6: 5.38
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	00 3c 37             	add    BYTE PTR [rdi+rsi*1],bh
   3:	00 7c 37 01          	add    BYTE PTR [rdi+rsi*1+0x1],bh
   7:	00 7c 37 02          	add    BYTE PTR [rdi+rsi*1+0x2],bh
   b:	00 7c 37 03          	add    BYTE PTR [rdi+rsi*1+0x3],bh
   f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  16:	0f 1f 84 00 00 00 00 
  1d:	00 
  1e:	00 7c 37 04          	add    BYTE PTR [rdi+rsi*1+0x4],bh
  22:	00 7c 37 05          	add    BYTE PTR [rdi+rsi*1+0x5],bh
  26:	00 7c 37 06          	add    BYTE PTR [rdi+rsi*1+0x6],bh
  2a:	00 7c 37 07          	add    BYTE PTR [rdi+rsi*1+0x7],bh
  2e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  35:	0f 1f 84 00 00 00 00 
  3c:	00 
  3d:	00 7c 37 08          	add    BYTE PTR [rdi+rsi*1+0x8],bh
  41:	00 7c 37 09          	add    BYTE PTR [rdi+rsi*1+0x9],bh
  45:	00 7c 37 0a          	add    BYTE PTR [rdi+rsi*1+0xa],bh
  49:	00 7c 37 0b          	add    BYTE PTR [rdi+rsi*1+0xb],bh
  4d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  54:	0f 1f 84 00 00 00 00 
  5b:	00 
  5c:	00 7c 37 0c          	add    BYTE PTR [rdi+rsi*1+0xc],bh
  60:	00 7c 37 0d          	add    BYTE PTR [rdi+rsi*1+0xd],bh
  64:	00 7c 37 0e          	add    BYTE PTR [rdi+rsi*1+0xe],bh
  68:	00 7c 37 0f          	add    BYTE PTR [rdi+rsi*1+0xf],bh
  6c:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 nop WORD PTR cs:[rax+rax*1+0x0]
  73:	0f 1f 84 00 00 00 00 
  7a:	00

Init:
```
MOV BH, 0;
XOR RSI, RSI
```
Show nanoBench command
Results:
- Instructions retired: 20.2
- Core cycles: 16.32
- Reference cycles: 14.52
- UOPS_EXECUTED.CORE: 64.11
- RETIRE_SLOTS: 52.1
- UOPS_MITE: 0.36
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.16
- UOPS_PORT_1: 4.89
- UOPS_PORT_2: 16.01
- UOPS_PORT_3: 16.0
- UOPS_PORT_4: 16.06
- UOPS_PORT_5: 1.86
- UOPS_PORT_6: 5.38
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

ADD (M8, R8h) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (long NOPs)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (long NOPs)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (long NOPs)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (long NOPs)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (long NOPs)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (long NOPs)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (long NOPs)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (long NOPs)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)