VSUBPS (YMM, YMM, YMM)

With unroll_count=500 and no inner loop

Code:

   0:	c5 f4 5c c2          	vsubps ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.0
- UOPS_EXECUTED.CORE: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c5 f4 5c c2          	vsubps ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 1.0
- UOPS_EXECUTED.CORE: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c5 f4 5c c2          	vsubps ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 1.0
- UOPS_EXECUTED.CORE: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c5 f4 5c c2          	vsubps ymm0,ymm1,ymm2
   4:	c5 f4 5c da          	vsubps ymm3,ymm1,ymm2
   8:	c5 f4 5c e2          	vsubps ymm4,ymm1,ymm2
   c:	c5 f4 5c ea          	vsubps ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.97
- UOPS_EXECUTED.CORE: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c5 f4 5c c2          	vsubps ymm0,ymm1,ymm2
   4:	c5 f4 5c da          	vsubps ymm3,ymm1,ymm2
   8:	c5 f4 5c e2          	vsubps ymm4,ymm1,ymm2
   c:	c5 f4 5c ea          	vsubps ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 4.0
- UOPS_EXECUTED.CORE: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c5 f4 5c c2          	vsubps ymm0,ymm1,ymm2
   4:	c5 f4 5c da          	vsubps ymm3,ymm1,ymm2
   8:	c5 f4 5c e2          	vsubps ymm4,ymm1,ymm2
   c:	c5 f4 5c ea          	vsubps ymm5,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.0
- Reference cycles: 4.01
- UOPS_EXECUTED.CORE: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c5 f4 5c c2          	vsubps ymm0,ymm1,ymm2
   4:	c5 f4 5c da          	vsubps ymm3,ymm1,ymm2
   8:	c5 f4 5c e2          	vsubps ymm4,ymm1,ymm2
   c:	c5 f4 5c ea          	vsubps ymm5,ymm1,ymm2
  10:	c5 f4 5c f2          	vsubps ymm6,ymm1,ymm2
  14:	c5 f4 5c fa          	vsubps ymm7,ymm1,ymm2
  18:	c5 74 5c c2          	vsubps ymm8,ymm1,ymm2
  1c:	c5 74 5c ca          	vsubps ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 7.95
- UOPS_EXECUTED.CORE: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c5 f4 5c c2          	vsubps ymm0,ymm1,ymm2
   4:	c5 f4 5c da          	vsubps ymm3,ymm1,ymm2
   8:	c5 f4 5c e2          	vsubps ymm4,ymm1,ymm2
   c:	c5 f4 5c ea          	vsubps ymm5,ymm1,ymm2
  10:	c5 f4 5c f2          	vsubps ymm6,ymm1,ymm2
  14:	c5 f4 5c fa          	vsubps ymm7,ymm1,ymm2
  18:	c5 74 5c c2          	vsubps ymm8,ymm1,ymm2
  1c:	c5 74 5c ca          	vsubps ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.01
- Reference cycles: 8.0
- UOPS_EXECUTED.CORE: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	c5 f4 5c c2          	vsubps ymm0,ymm1,ymm2
   4:	c5 f4 5c da          	vsubps ymm3,ymm1,ymm2
   8:	c5 f4 5c e2          	vsubps ymm4,ymm1,ymm2
   c:	c5 f4 5c ea          	vsubps ymm5,ymm1,ymm2
  10:	c5 f4 5c f2          	vsubps ymm6,ymm1,ymm2
  14:	c5 f4 5c fa          	vsubps ymm7,ymm1,ymm2
  18:	c5 74 5c c2          	vsubps ymm8,ymm1,ymm2
  1c:	c5 74 5c ca          	vsubps ymm9,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.01
- Reference cycles: 8.03
- UOPS_EXECUTED.CORE: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 11 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c5 f4 5c c2          	vsubps ymm0,ymm1,ymm2
   4:	c5 f4 5c da          	vsubps ymm3,ymm1,ymm2
   8:	c5 f4 5c e2          	vsubps ymm4,ymm1,ymm2
   c:	c5 f4 5c ea          	vsubps ymm5,ymm1,ymm2
  10:	c5 f4 5c f2          	vsubps ymm6,ymm1,ymm2
  14:	c5 f4 5c fa          	vsubps ymm7,ymm1,ymm2
  18:	c5 74 5c c2          	vsubps ymm8,ymm1,ymm2
  1c:	c5 74 5c ca          	vsubps ymm9,ymm1,ymm2
  20:	c5 74 5c d2          	vsubps ymm10,ymm1,ymm2
  24:	c5 74 5c da          	vsubps ymm11,ymm1,ymm2
  28:	c5 74 5c e2          	vsubps ymm12,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.0
- Reference cycles: 10.88
- UOPS_EXECUTED.CORE: 11.0
- RETIRE_SLOTS: 11.0
- UOPS_MITE: 11.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 11.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.75

With loop_count=1000 and unroll_count=1

Code:

   0:	c5 f4 5c c2          	vsubps ymm0,ymm1,ymm2
   4:	c5 f4 5c da          	vsubps ymm3,ymm1,ymm2
   8:	c5 f4 5c e2          	vsubps ymm4,ymm1,ymm2
   c:	c5 f4 5c ea          	vsubps ymm5,ymm1,ymm2
  10:	c5 f4 5c f2          	vsubps ymm6,ymm1,ymm2
  14:	c5 f4 5c fa          	vsubps ymm7,ymm1,ymm2
  18:	c5 74 5c c2          	vsubps ymm8,ymm1,ymm2
  1c:	c5 74 5c ca          	vsubps ymm9,ymm1,ymm2
  20:	c5 74 5c d2          	vsubps ymm10,ymm1,ymm2
  24:	c5 74 5c da          	vsubps ymm11,ymm1,ymm2
  28:	c5 74 5c e2          	vsubps ymm12,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 11.01
- Reference cycles: 11.02
- UOPS_EXECUTED.CORE: 12.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 11.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c5 f4 5c c2          	vsubps ymm0,ymm1,ymm2
   4:	c5 f4 5c da          	vsubps ymm3,ymm1,ymm2
   8:	c5 f4 5c e2          	vsubps ymm4,ymm1,ymm2
   c:	c5 f4 5c ea          	vsubps ymm5,ymm1,ymm2
  10:	c5 f4 5c f2          	vsubps ymm6,ymm1,ymm2
  14:	c5 f4 5c fa          	vsubps ymm7,ymm1,ymm2
  18:	c5 74 5c c2          	vsubps ymm8,ymm1,ymm2
  1c:	c5 74 5c ca          	vsubps ymm9,ymm1,ymm2
  20:	c5 74 5c d2          	vsubps ymm10,ymm1,ymm2
  24:	c5 74 5c da          	vsubps ymm11,ymm1,ymm2
  28:	c5 74 5c e2          	vsubps ymm12,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 11.2
- Core cycles: 11.01
- Reference cycles: 10.99
- UOPS_EXECUTED.CORE: 11.1
- RETIRE_SLOTS: 11.1
- UOPS_MITE: 0.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 11.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With the same register for for different operands

With unroll_count=500 and no inner loop

Code:

   0:	c5 fc 5c c0          	vsubps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 2.98
- UOPS_EXECUTED.CORE: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	c5 fc 5c c0          	vsubps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 3.0
- Reference cycles: 3.0
- UOPS_EXECUTED.CORE: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c5 fc 5c c0          	vsubps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 3.0
- Reference cycles: 3.0
- UOPS_EXECUTED.CORE: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

VSUBPS (YMM, YMM, YMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 11 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100