CMPXCHG_LOCK (M16, R16) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 22.0
  • Reference cycles: 21.31
  • UOPS_EXECUTED.THREAD: 9.0
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 9.0
  • UOPS_PORT_0: 1.31
  • UOPS_PORT_1: 1.3
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 3.39
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     6:	90                   	nop
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 22.0
  • Reference cycles: 21.31
  • UOPS_EXECUTED.THREAD: 9.0
  • RETIRE_SLOTS: 10.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 9.0
  • UOPS_PORT_0: 1.5
  • UOPS_PORT_1: 1.44
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 3.06
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 22.0
  • Reference cycles: 21.33
  • UOPS_EXECUTED.THREAD: 9.1
  • RETIRE_SLOTS: 9.1
  • UOPS_MITE: 0.1
  • UOPS_MS: 9.01
  • UOPS_PORT_0: 1.3
  • UOPS_PORT_1: 1.31
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 3.48
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.1

With loop_count=100 and unroll_count=100

• Code:

     0:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 22.0
  • Reference cycles: 21.33
  • UOPS_EXECUTED.THREAD: 9.01
  • RETIRE_SLOTS: 9.01
  • UOPS_MITE: 0.01
  • UOPS_MS: 9.01
  • UOPS_PORT_0: 1.31
  • UOPS_PORT_1: 1.29
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 3.41
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 22.0
  • Reference cycles: 21.38
  • UOPS_EXECUTED.THREAD: 9.0
  • RETIRE_SLOTS: 10.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 9.0
  • UOPS_PORT_0: 2.02
  • UOPS_PORT_1: 2.09
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 3.67
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.2
  • Core cycles: 22.0
  • Reference cycles: 21.33
  • UOPS_EXECUTED.THREAD: 9.1
  • RETIRE_SLOTS: 10.1
  • UOPS_MITE: 1.1
  • UOPS_MS: 9.01
  • UOPS_PORT_0: 2.06
  • UOPS_PORT_1: 1.99
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 4.13
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.1

With loop_count=100 and unroll_count=100

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.02
  • Core cycles: 22.0
  • Reference cycles: 21.33
  • UOPS_EXECUTED.THREAD: 9.01
  • RETIRE_SLOTS: 10.01
  • UOPS_MITE: 1.01
  • UOPS_MS: 9.01
  • UOPS_PORT_0: 2.03
  • UOPS_PORT_1: 1.96
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 4.08
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.01

With unroll_count=200 and no inner loop

• Code:

     0:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     6:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
     d:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    14:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 100.0
  • Reference cycles: 96.96
  • UOPS_EXECUTED.THREAD: 36.0
  • RETIRE_SLOTS: 36.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 36.0
  • UOPS_PORT_0: 9.22
  • UOPS_PORT_1: 8.7
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 17.54
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     6:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
     d:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    14:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 97.0
  • Reference cycles: 94.06
  • UOPS_EXECUTED.THREAD: 36.5
  • RETIRE_SLOTS: 36.5
  • UOPS_MITE: 0.5
  • UOPS_MS: 36.03
  • UOPS_PORT_0: 8.62
  • UOPS_PORT_1: 8.45
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 17.43
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With loop_count=100 and unroll_count=20

• Code:

     0:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     6:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
     d:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    14:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 99.7
  • Reference cycles: 96.69
  • UOPS_EXECUTED.THREAD: 36.05
  • RETIRE_SLOTS: 36.05
  • UOPS_MITE: 0.05
  • UOPS_MS: 36.03
  • UOPS_PORT_0: 9.12
  • UOPS_PORT_1: 8.67
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 17.51
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.05

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     9:	48 31 c0             	xor    rax,rax
     c:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
    13:	48 31 c0             	xor    rax,rax
    16:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    1d:	48 31 c0             	xor    rax,rax
    20:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 100.0
  • Reference cycles: 97.01
  • UOPS_EXECUTED.THREAD: 36.0
  • RETIRE_SLOTS: 40.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 36.0
  • UOPS_PORT_0: 15.78
  • UOPS_PORT_1: 15.77
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 22.75
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     9:	48 31 c0             	xor    rax,rax
     c:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
    13:	48 31 c0             	xor    rax,rax
    16:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    1d:	48 31 c0             	xor    rax,rax
    20:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 9.0
  • Core cycles: 97.0
  • Reference cycles: 94.06
  • UOPS_EXECUTED.THREAD: 36.5
  • RETIRE_SLOTS: 40.5
  • UOPS_MITE: 4.5
  • UOPS_MS: 36.03
  • UOPS_PORT_0: 15.04
  • UOPS_PORT_1: 14.64
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 23.28
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.5

With loop_count=100 and unroll_count=20

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     9:	48 31 c0             	xor    rax,rax
     c:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
    13:	48 31 c0             	xor    rax,rax
    16:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    1d:	48 31 c0             	xor    rax,rax
    20:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.1
  • Core cycles: 99.7
  • Reference cycles: 96.69
  • UOPS_EXECUTED.THREAD: 36.05
  • RETIRE_SLOTS: 40.05
  • UOPS_MITE: 4.05
  • UOPS_MS: 36.03
  • UOPS_PORT_0: 15.37
  • UOPS_PORT_1: 14.71
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 23.38
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.05

With unroll_count=100 and no inner loop

• Code:

     0:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     6:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
     d:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    14:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
    1b:	66 f0 45 0f b1 46 08 	lock cmpxchg WORD PTR [r14+0x8],r8w
    22:	66 f0 45 0f b1 46 0a 	lock cmpxchg WORD PTR [r14+0xa],r8w
    29:	66 f0 45 0f b1 46 0c 	lock cmpxchg WORD PTR [r14+0xc],r8w
    30:	66 f0 45 0f b1 46 0e 	lock cmpxchg WORD PTR [r14+0xe],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 200.0
  • Reference cycles: 193.97
  • UOPS_EXECUTED.THREAD: 72.0
  • RETIRE_SLOTS: 72.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 72.0
  • UOPS_PORT_0: 18.47
  • UOPS_PORT_1: 17.38
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 35.07
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     6:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
     d:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    14:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
    1b:	66 f0 45 0f b1 46 08 	lock cmpxchg WORD PTR [r14+0x8],r8w
    22:	66 f0 45 0f b1 46 0a 	lock cmpxchg WORD PTR [r14+0xa],r8w
    29:	66 f0 45 0f b1 46 0c 	lock cmpxchg WORD PTR [r14+0xc],r8w
    30:	66 f0 45 0f b1 46 0e 	lock cmpxchg WORD PTR [r14+0xe],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 194.01
  • Reference cycles: 188.12
  • UOPS_EXECUTED.THREAD: 73.0
  • RETIRE_SLOTS: 73.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 72.06
  • UOPS_PORT_0: 17.24
  • UOPS_PORT_1: 16.9
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 34.85
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=10

• Code:

     0:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     6:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
     d:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    14:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
    1b:	66 f0 45 0f b1 46 08 	lock cmpxchg WORD PTR [r14+0x8],r8w
    22:	66 f0 45 0f b1 46 0a 	lock cmpxchg WORD PTR [r14+0xa],r8w
    29:	66 f0 45 0f b1 46 0c 	lock cmpxchg WORD PTR [r14+0xc],r8w
    30:	66 f0 45 0f b1 46 0e 	lock cmpxchg WORD PTR [r14+0xe],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 199.41
  • Reference cycles: 193.38
  • UOPS_EXECUTED.THREAD: 72.1
  • RETIRE_SLOTS: 72.1
  • UOPS_MITE: 0.1
  • UOPS_MS: 72.06
  • UOPS_PORT_0: 18.24
  • UOPS_PORT_1: 17.35
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 35.02
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.1

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     9:	48 31 c0             	xor    rax,rax
     c:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
    13:	48 31 c0             	xor    rax,rax
    16:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    1d:	48 31 c0             	xor    rax,rax
    20:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
    27:	48 31 c0             	xor    rax,rax
    2a:	66 f0 45 0f b1 46 08 	lock cmpxchg WORD PTR [r14+0x8],r8w
    31:	48 31 c0             	xor    rax,rax
    34:	66 f0 45 0f b1 46 0a 	lock cmpxchg WORD PTR [r14+0xa],r8w
    3b:	48 31 c0             	xor    rax,rax
    3e:	66 f0 45 0f b1 46 0c 	lock cmpxchg WORD PTR [r14+0xc],r8w
    45:	48 31 c0             	xor    rax,rax
    48:	66 f0 45 0f b1 46 0e 	lock cmpxchg WORD PTR [r14+0xe],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 16.0
  • Core cycles: 199.99
  • Reference cycles: 193.97
  • UOPS_EXECUTED.THREAD: 72.0
  • RETIRE_SLOTS: 80.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 72.0
  • UOPS_PORT_0: 30.64
  • UOPS_PORT_1: 30.24
  • UOPS_PORT_2: 7.98
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 43.19
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     9:	48 31 c0             	xor    rax,rax
     c:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
    13:	48 31 c0             	xor    rax,rax
    16:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    1d:	48 31 c0             	xor    rax,rax
    20:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
    27:	48 31 c0             	xor    rax,rax
    2a:	66 f0 45 0f b1 46 08 	lock cmpxchg WORD PTR [r14+0x8],r8w
    31:	48 31 c0             	xor    rax,rax
    34:	66 f0 45 0f b1 46 0a 	lock cmpxchg WORD PTR [r14+0xa],r8w
    3b:	48 31 c0             	xor    rax,rax
    3e:	66 f0 45 0f b1 46 0c 	lock cmpxchg WORD PTR [r14+0xc],r8w
    45:	48 31 c0             	xor    rax,rax
    48:	66 f0 45 0f b1 46 0e 	lock cmpxchg WORD PTR [r14+0xe],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 194.01
  • Reference cycles: 188.13
  • UOPS_EXECUTED.THREAD: 73.0
  • RETIRE_SLOTS: 81.0
  • UOPS_MITE: 9.01
  • UOPS_MS: 72.05
  • UOPS_PORT_0: 30.11
  • UOPS_PORT_1: 29.27
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 46.56
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 9.01

With loop_count=100 and unroll_count=10

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     9:	48 31 c0             	xor    rax,rax
     c:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
    13:	48 31 c0             	xor    rax,rax
    16:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    1d:	48 31 c0             	xor    rax,rax
    20:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
    27:	48 31 c0             	xor    rax,rax
    2a:	66 f0 45 0f b1 46 08 	lock cmpxchg WORD PTR [r14+0x8],r8w
    31:	48 31 c0             	xor    rax,rax
    34:	66 f0 45 0f b1 46 0a 	lock cmpxchg WORD PTR [r14+0xa],r8w
    3b:	48 31 c0             	xor    rax,rax
    3e:	66 f0 45 0f b1 46 0c 	lock cmpxchg WORD PTR [r14+0xc],r8w
    45:	48 31 c0             	xor    rax,rax
    48:	66 f0 45 0f b1 46 0e 	lock cmpxchg WORD PTR [r14+0xe],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 199.41
  • Reference cycles: 193.37
  • UOPS_EXECUTED.THREAD: 72.1
  • RETIRE_SLOTS: 80.1
  • UOPS_MITE: 8.11
  • UOPS_MS: 72.05
  • UOPS_PORT_0: 30.74
  • UOPS_PORT_1: 29.42
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 46.73
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.11

With unroll_count=100 and no inner loop

• Code:

     0:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     6:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
     d:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    14:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
    1b:	66 f0 45 0f b1 46 08 	lock cmpxchg WORD PTR [r14+0x8],r8w
    22:	66 f0 45 0f b1 46 0a 	lock cmpxchg WORD PTR [r14+0xa],r8w
    29:	66 f0 45 0f b1 46 0c 	lock cmpxchg WORD PTR [r14+0xc],r8w
    30:	66 f0 45 0f b1 46 0e 	lock cmpxchg WORD PTR [r14+0xe],r8w
    37:	66 f0 45 0f b1 46 10 	lock cmpxchg WORD PTR [r14+0x10],r8w
    3e:	66 f0 45 0f b1 46 12 	lock cmpxchg WORD PTR [r14+0x12],r8w
    45:	66 f0 45 0f b1 46 14 	lock cmpxchg WORD PTR [r14+0x14],r8w
    4c:	66 f0 45 0f b1 46 16 	lock cmpxchg WORD PTR [r14+0x16],r8w
    53:	66 f0 45 0f b1 46 18 	lock cmpxchg WORD PTR [r14+0x18],r8w
    5a:	66 f0 45 0f b1 46 1a 	lock cmpxchg WORD PTR [r14+0x1a],r8w
    61:	66 f0 45 0f b1 46 1c 	lock cmpxchg WORD PTR [r14+0x1c],r8w
    68:	66 f0 45 0f b1 46 1e 	lock cmpxchg WORD PTR [r14+0x1e],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 16.0
  • Core cycles: 400.0
  • Reference cycles: 387.89
  • UOPS_EXECUTED.THREAD: 144.0
  • RETIRE_SLOTS: 144.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 144.0
  • UOPS_PORT_0: 36.85
  • UOPS_PORT_1: 34.8
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 70.06
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     6:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
     d:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    14:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
    1b:	66 f0 45 0f b1 46 08 	lock cmpxchg WORD PTR [r14+0x8],r8w
    22:	66 f0 45 0f b1 46 0a 	lock cmpxchg WORD PTR [r14+0xa],r8w
    29:	66 f0 45 0f b1 46 0c 	lock cmpxchg WORD PTR [r14+0xc],r8w
    30:	66 f0 45 0f b1 46 0e 	lock cmpxchg WORD PTR [r14+0xe],r8w
    37:	66 f0 45 0f b1 46 10 	lock cmpxchg WORD PTR [r14+0x10],r8w
    3e:	66 f0 45 0f b1 46 12 	lock cmpxchg WORD PTR [r14+0x12],r8w
    45:	66 f0 45 0f b1 46 14 	lock cmpxchg WORD PTR [r14+0x14],r8w
    4c:	66 f0 45 0f b1 46 16 	lock cmpxchg WORD PTR [r14+0x16],r8w
    53:	66 f0 45 0f b1 46 18 	lock cmpxchg WORD PTR [r14+0x18],r8w
    5a:	66 f0 45 0f b1 46 1a 	lock cmpxchg WORD PTR [r14+0x1a],r8w
    61:	66 f0 45 0f b1 46 1c 	lock cmpxchg WORD PTR [r14+0x1c],r8w
    68:	66 f0 45 0f b1 46 1e 	lock cmpxchg WORD PTR [r14+0x1e],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 394.01
  • Reference cycles: 382.08
  • UOPS_EXECUTED.THREAD: 145.0
  • RETIRE_SLOTS: 145.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 144.06
  • UOPS_PORT_0: 35.51
  • UOPS_PORT_1: 34.2
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 69.99
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=10

• Code:

     0:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     6:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
     d:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    14:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
    1b:	66 f0 45 0f b1 46 08 	lock cmpxchg WORD PTR [r14+0x8],r8w
    22:	66 f0 45 0f b1 46 0a 	lock cmpxchg WORD PTR [r14+0xa],r8w
    29:	66 f0 45 0f b1 46 0c 	lock cmpxchg WORD PTR [r14+0xc],r8w
    30:	66 f0 45 0f b1 46 0e 	lock cmpxchg WORD PTR [r14+0xe],r8w
    37:	66 f0 45 0f b1 46 10 	lock cmpxchg WORD PTR [r14+0x10],r8w
    3e:	66 f0 45 0f b1 46 12 	lock cmpxchg WORD PTR [r14+0x12],r8w
    45:	66 f0 45 0f b1 46 14 	lock cmpxchg WORD PTR [r14+0x14],r8w
    4c:	66 f0 45 0f b1 46 16 	lock cmpxchg WORD PTR [r14+0x16],r8w
    53:	66 f0 45 0f b1 46 18 	lock cmpxchg WORD PTR [r14+0x18],r8w
    5a:	66 f0 45 0f b1 46 1a 	lock cmpxchg WORD PTR [r14+0x1a],r8w
    61:	66 f0 45 0f b1 46 1c 	lock cmpxchg WORD PTR [r14+0x1c],r8w
    68:	66 f0 45 0f b1 46 1e 	lock cmpxchg WORD PTR [r14+0x1e],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 399.41
  • Reference cycles: 387.31
  • UOPS_EXECUTED.THREAD: 144.1
  • RETIRE_SLOTS: 144.1
  • UOPS_MITE: 0.1
  • UOPS_MS: 144.06
  • UOPS_PORT_0: 36.75
  • UOPS_PORT_1: 34.64
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 70.13
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.1

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     9:	48 31 c0             	xor    rax,rax
     c:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
    13:	48 31 c0             	xor    rax,rax
    16:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    1d:	48 31 c0             	xor    rax,rax
    20:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
    27:	48 31 c0             	xor    rax,rax
    2a:	66 f0 45 0f b1 46 08 	lock cmpxchg WORD PTR [r14+0x8],r8w
    31:	48 31 c0             	xor    rax,rax
    34:	66 f0 45 0f b1 46 0a 	lock cmpxchg WORD PTR [r14+0xa],r8w
    3b:	48 31 c0             	xor    rax,rax
    3e:	66 f0 45 0f b1 46 0c 	lock cmpxchg WORD PTR [r14+0xc],r8w
    45:	48 31 c0             	xor    rax,rax
    48:	66 f0 45 0f b1 46 0e 	lock cmpxchg WORD PTR [r14+0xe],r8w
    4f:	48 31 c0             	xor    rax,rax
    52:	66 f0 45 0f b1 46 10 	lock cmpxchg WORD PTR [r14+0x10],r8w
    59:	48 31 c0             	xor    rax,rax
    5c:	66 f0 45 0f b1 46 12 	lock cmpxchg WORD PTR [r14+0x12],r8w
    63:	48 31 c0             	xor    rax,rax
    66:	66 f0 45 0f b1 46 14 	lock cmpxchg WORD PTR [r14+0x14],r8w
    6d:	48 31 c0             	xor    rax,rax
    70:	66 f0 45 0f b1 46 16 	lock cmpxchg WORD PTR [r14+0x16],r8w
    77:	48 31 c0             	xor    rax,rax
    7a:	66 f0 45 0f b1 46 18 	lock cmpxchg WORD PTR [r14+0x18],r8w
    81:	48 31 c0             	xor    rax,rax
    84:	66 f0 45 0f b1 46 1a 	lock cmpxchg WORD PTR [r14+0x1a],r8w
    8b:	48 31 c0             	xor    rax,rax
    8e:	66 f0 45 0f b1 46 1c 	lock cmpxchg WORD PTR [r14+0x1c],r8w
    95:	48 31 c0             	xor    rax,rax
    98:	66 f0 45 0f b1 46 1e 	lock cmpxchg WORD PTR [r14+0x1e],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 32.0
  • Core cycles: 399.99
  • Reference cycles: 387.84
  • UOPS_EXECUTED.THREAD: 144.0
  • RETIRE_SLOTS: 160.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 144.0
  • UOPS_PORT_0: 48.9
  • UOPS_PORT_1: 48.28
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 73.61
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     9:	48 31 c0             	xor    rax,rax
     c:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
    13:	48 31 c0             	xor    rax,rax
    16:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    1d:	48 31 c0             	xor    rax,rax
    20:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
    27:	48 31 c0             	xor    rax,rax
    2a:	66 f0 45 0f b1 46 08 	lock cmpxchg WORD PTR [r14+0x8],r8w
    31:	48 31 c0             	xor    rax,rax
    34:	66 f0 45 0f b1 46 0a 	lock cmpxchg WORD PTR [r14+0xa],r8w
    3b:	48 31 c0             	xor    rax,rax
    3e:	66 f0 45 0f b1 46 0c 	lock cmpxchg WORD PTR [r14+0xc],r8w
    45:	48 31 c0             	xor    rax,rax
    48:	66 f0 45 0f b1 46 0e 	lock cmpxchg WORD PTR [r14+0xe],r8w
    4f:	48 31 c0             	xor    rax,rax
    52:	66 f0 45 0f b1 46 10 	lock cmpxchg WORD PTR [r14+0x10],r8w
    59:	48 31 c0             	xor    rax,rax
    5c:	66 f0 45 0f b1 46 12 	lock cmpxchg WORD PTR [r14+0x12],r8w
    63:	48 31 c0             	xor    rax,rax
    66:	66 f0 45 0f b1 46 14 	lock cmpxchg WORD PTR [r14+0x14],r8w
    6d:	48 31 c0             	xor    rax,rax
    70:	66 f0 45 0f b1 46 16 	lock cmpxchg WORD PTR [r14+0x16],r8w
    77:	48 31 c0             	xor    rax,rax
    7a:	66 f0 45 0f b1 46 18 	lock cmpxchg WORD PTR [r14+0x18],r8w
    81:	48 31 c0             	xor    rax,rax
    84:	66 f0 45 0f b1 46 1a 	lock cmpxchg WORD PTR [r14+0x1a],r8w
    8b:	48 31 c0             	xor    rax,rax
    8e:	66 f0 45 0f b1 46 1c 	lock cmpxchg WORD PTR [r14+0x1c],r8w
    95:	48 31 c0             	xor    rax,rax
    98:	66 f0 45 0f b1 46 1e 	lock cmpxchg WORD PTR [r14+0x1e],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 34.0
  • Core cycles: 394.01
  • Reference cycles: 382.08
  • UOPS_EXECUTED.THREAD: 145.0
  • RETIRE_SLOTS: 161.0
  • UOPS_MITE: 17.01
  • UOPS_MS: 144.05
  • UOPS_PORT_0: 47.01
  • UOPS_PORT_1: 45.7
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 80.36
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 17.01

With loop_count=100 and unroll_count=10

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 45 0f b1 06    	lock cmpxchg WORD PTR [r14],r8w
     9:	48 31 c0             	xor    rax,rax
     c:	66 f0 45 0f b1 46 02 	lock cmpxchg WORD PTR [r14+0x2],r8w
    13:	48 31 c0             	xor    rax,rax
    16:	66 f0 45 0f b1 46 04 	lock cmpxchg WORD PTR [r14+0x4],r8w
    1d:	48 31 c0             	xor    rax,rax
    20:	66 f0 45 0f b1 46 06 	lock cmpxchg WORD PTR [r14+0x6],r8w
    27:	48 31 c0             	xor    rax,rax
    2a:	66 f0 45 0f b1 46 08 	lock cmpxchg WORD PTR [r14+0x8],r8w
    31:	48 31 c0             	xor    rax,rax
    34:	66 f0 45 0f b1 46 0a 	lock cmpxchg WORD PTR [r14+0xa],r8w
    3b:	48 31 c0             	xor    rax,rax
    3e:	66 f0 45 0f b1 46 0c 	lock cmpxchg WORD PTR [r14+0xc],r8w
    45:	48 31 c0             	xor    rax,rax
    48:	66 f0 45 0f b1 46 0e 	lock cmpxchg WORD PTR [r14+0xe],r8w
    4f:	48 31 c0             	xor    rax,rax
    52:	66 f0 45 0f b1 46 10 	lock cmpxchg WORD PTR [r14+0x10],r8w
    59:	48 31 c0             	xor    rax,rax
    5c:	66 f0 45 0f b1 46 12 	lock cmpxchg WORD PTR [r14+0x12],r8w
    63:	48 31 c0             	xor    rax,rax
    66:	66 f0 45 0f b1 46 14 	lock cmpxchg WORD PTR [r14+0x14],r8w
    6d:	48 31 c0             	xor    rax,rax
    70:	66 f0 45 0f b1 46 16 	lock cmpxchg WORD PTR [r14+0x16],r8w
    77:	48 31 c0             	xor    rax,rax
    7a:	66 f0 45 0f b1 46 18 	lock cmpxchg WORD PTR [r14+0x18],r8w
    81:	48 31 c0             	xor    rax,rax
    84:	66 f0 45 0f b1 46 1a 	lock cmpxchg WORD PTR [r14+0x1a],r8w
    8b:	48 31 c0             	xor    rax,rax
    8e:	66 f0 45 0f b1 46 1c 	lock cmpxchg WORD PTR [r14+0x1c],r8w
    95:	48 31 c0             	xor    rax,rax
    98:	66 f0 45 0f b1 46 1e 	lock cmpxchg WORD PTR [r14+0x1e],r8w
  

• Show nanoBench command
• Results:
  • Instructions retired: 32.2
  • Core cycles: 399.41
  • Reference cycles: 387.31
  • UOPS_EXECUTED.THREAD: 144.1
  • RETIRE_SLOTS: 160.1
  • UOPS_MITE: 16.11
  • UOPS_MS: 144.05
  • UOPS_PORT_0: 47.83
  • UOPS_PORT_1: 46.09
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 80.49
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.11

With unroll_count=500 and no inner loop

• Code:

     0:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 22.0
  • Reference cycles: 21.33
  • UOPS_EXECUTED.THREAD: 9.0
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 9.0
  • UOPS_PORT_0: 1.33
  • UOPS_PORT_1: 1.27
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 3.4
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     7:	90                   	nop
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 22.0
  • Reference cycles: 24.27
  • UOPS_EXECUTED.THREAD: 9.0
  • RETIRE_SLOTS: 10.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 9.0
  • UOPS_PORT_0: 1.54
  • UOPS_PORT_1: 1.42
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 3.05
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 22.0
  • Reference cycles: 24.28
  • UOPS_EXECUTED.THREAD: 9.1
  • RETIRE_SLOTS: 9.1
  • UOPS_MITE: 0.1
  • UOPS_MS: 9.01
  • UOPS_PORT_0: 1.31
  • UOPS_PORT_1: 1.3
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 3.48
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.1

With loop_count=100 and unroll_count=100

• Code:

     0:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 22.0
  • Reference cycles: 24.28
  • UOPS_EXECUTED.THREAD: 9.01
  • RETIRE_SLOTS: 9.01
  • UOPS_MITE: 0.01
  • UOPS_MS: 9.01
  • UOPS_PORT_0: 1.31
  • UOPS_PORT_1: 1.29
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 3.41
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 22.0
  • Reference cycles: 24.27
  • UOPS_EXECUTED.THREAD: 9.0
  • RETIRE_SLOTS: 10.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 9.0
  • UOPS_PORT_0: 2.01
  • UOPS_PORT_1: 2.07
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 3.69
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 2.2
  • Core cycles: 22.0
  • Reference cycles: 24.28
  • UOPS_EXECUTED.THREAD: 9.1
  • RETIRE_SLOTS: 10.1
  • UOPS_MITE: 1.1
  • UOPS_MS: 9.01
  • UOPS_PORT_0: 2.05
  • UOPS_PORT_1: 1.98
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 4.12
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.1

With loop_count=100 and unroll_count=100

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 2.02
  • Core cycles: 22.0
  • Reference cycles: 24.28
  • UOPS_EXECUTED.THREAD: 9.01
  • RETIRE_SLOTS: 10.01
  • UOPS_MITE: 1.01
  • UOPS_MS: 9.01
  • UOPS_PORT_0: 2.02
  • UOPS_PORT_1: 1.97
  • UOPS_PORT_2: 1.0
  • UOPS_PORT_3: 1.0
  • UOPS_PORT_4: 1.0
  • UOPS_PORT_5: 4.08
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.01

With unroll_count=200 and no inner loop

• Code:

     0:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     7:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
     e:	02 
     f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    16:	04 
    17:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    1e:	06 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 100.0
  • Reference cycles: 110.35
  • UOPS_EXECUTED.THREAD: 36.0
  • RETIRE_SLOTS: 36.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 36.0
  • UOPS_PORT_0: 9.29
  • UOPS_PORT_1: 8.68
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 17.52
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     7:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
     e:	02 
     f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    16:	04 
    17:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    1e:	06 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 97.0
  • Reference cycles: 107.04
  • UOPS_EXECUTED.THREAD: 36.5
  • RETIRE_SLOTS: 36.5
  • UOPS_MITE: 0.5
  • UOPS_MS: 36.03
  • UOPS_PORT_0: 8.59
  • UOPS_PORT_1: 8.44
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 17.43
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.5

With loop_count=100 and unroll_count=20

• Code:

     0:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     7:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
     e:	02 
     f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    16:	04 
    17:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    1e:	06 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 99.7
  • Reference cycles: 110.02
  • UOPS_EXECUTED.THREAD: 36.05
  • RETIRE_SLOTS: 36.05
  • UOPS_MITE: 0.05
  • UOPS_MS: 36.03
  • UOPS_PORT_0: 9.14
  • UOPS_PORT_1: 8.66
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 17.52
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.05

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     a:	48 31 c0             	xor    rax,rax
     d:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
    14:	02 
    15:	48 31 c0             	xor    rax,rax
    18:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    1f:	04 
    20:	48 31 c0             	xor    rax,rax
    23:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    2a:	06 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 100.0
  • Reference cycles: 110.32
  • UOPS_EXECUTED.THREAD: 36.0
  • RETIRE_SLOTS: 40.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 36.0
  • UOPS_PORT_0: 14.4
  • UOPS_PORT_1: 13.39
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 26.25
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     a:	48 31 c0             	xor    rax,rax
     d:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
    14:	02 
    15:	48 31 c0             	xor    rax,rax
    18:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    1f:	04 
    20:	48 31 c0             	xor    rax,rax
    23:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    2a:	06 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 9.0
  • Core cycles: 97.0
  • Reference cycles: 107.03
  • UOPS_EXECUTED.THREAD: 36.5
  • RETIRE_SLOTS: 40.5
  • UOPS_MITE: 4.5
  • UOPS_MS: 36.02
  • UOPS_PORT_0: 14.99
  • UOPS_PORT_1: 14.64
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 23.3
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.5

With loop_count=100 and unroll_count=20

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     a:	48 31 c0             	xor    rax,rax
     d:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
    14:	02 
    15:	48 31 c0             	xor    rax,rax
    18:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    1f:	04 
    20:	48 31 c0             	xor    rax,rax
    23:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    2a:	06 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.1
  • Core cycles: 99.7
  • Reference cycles: 110.02
  • UOPS_EXECUTED.THREAD: 36.05
  • RETIRE_SLOTS: 40.05
  • UOPS_MITE: 4.05
  • UOPS_MS: 36.03
  • UOPS_PORT_0: 15.29
  • UOPS_PORT_1: 14.65
  • UOPS_PORT_2: 4.0
  • UOPS_PORT_3: 4.0
  • UOPS_PORT_4: 4.0
  • UOPS_PORT_5: 23.31
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.05

With unroll_count=100 and no inner loop

• Code:

     0:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     7:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
     e:	02 
     f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    16:	04 
    17:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    1e:	06 
    1f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x8],r8w
    26:	08 
    27:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xa],r8w
    2e:	0a 
    2f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xc],r8w
    36:	0c 
    37:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xe],r8w
    3e:	0e 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 200.0
  • Reference cycles: 220.75
  • UOPS_EXECUTED.THREAD: 72.0
  • RETIRE_SLOTS: 72.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 72.0
  • UOPS_PORT_0: 18.61
  • UOPS_PORT_1: 17.34
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 35.03
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     7:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
     e:	02 
     f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    16:	04 
    17:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    1e:	06 
    1f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x8],r8w
    26:	08 
    27:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xa],r8w
    2e:	0a 
    2f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xc],r8w
    36:	0c 
    37:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xe],r8w
    3e:	0e 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 194.01
  • Reference cycles: 214.08
  • UOPS_EXECUTED.THREAD: 73.0
  • RETIRE_SLOTS: 73.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 72.06
  • UOPS_PORT_0: 17.22
  • UOPS_PORT_1: 16.89
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 34.86
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=10

• Code:

     0:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     7:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
     e:	02 
     f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    16:	04 
    17:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    1e:	06 
    1f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x8],r8w
    26:	08 
    27:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xa],r8w
    2e:	0a 
    2f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xc],r8w
    36:	0c 
    37:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xe],r8w
    3e:	0e 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 199.4
  • Reference cycles: 220.03
  • UOPS_EXECUTED.THREAD: 72.1
  • RETIRE_SLOTS: 72.1
  • UOPS_MITE: 0.1
  • UOPS_MS: 72.06
  • UOPS_PORT_0: 18.26
  • UOPS_PORT_1: 17.34
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 35.04
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.1

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     a:	48 31 c0             	xor    rax,rax
     d:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
    14:	02 
    15:	48 31 c0             	xor    rax,rax
    18:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    1f:	04 
    20:	48 31 c0             	xor    rax,rax
    23:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    2a:	06 
    2b:	48 31 c0             	xor    rax,rax
    2e:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x8],r8w
    35:	08 
    36:	48 31 c0             	xor    rax,rax
    39:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xa],r8w
    40:	0a 
    41:	48 31 c0             	xor    rax,rax
    44:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xc],r8w
    4b:	0c 
    4c:	48 31 c0             	xor    rax,rax
    4f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xe],r8w
    56:	0e 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 16.0
  • Core cycles: 200.0
  • Reference cycles: 220.59
  • UOPS_EXECUTED.THREAD: 72.0
  • RETIRE_SLOTS: 80.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 72.0
  • UOPS_PORT_0: 31.14
  • UOPS_PORT_1: 30.47
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 51.39
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     a:	48 31 c0             	xor    rax,rax
     d:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
    14:	02 
    15:	48 31 c0             	xor    rax,rax
    18:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    1f:	04 
    20:	48 31 c0             	xor    rax,rax
    23:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    2a:	06 
    2b:	48 31 c0             	xor    rax,rax
    2e:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x8],r8w
    35:	08 
    36:	48 31 c0             	xor    rax,rax
    39:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xa],r8w
    40:	0a 
    41:	48 31 c0             	xor    rax,rax
    44:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xc],r8w
    4b:	0c 
    4c:	48 31 c0             	xor    rax,rax
    4f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xe],r8w
    56:	0e 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 194.01
  • Reference cycles: 214.08
  • UOPS_EXECUTED.THREAD: 73.0
  • RETIRE_SLOTS: 81.0
  • UOPS_MITE: 9.01
  • UOPS_MS: 72.05
  • UOPS_PORT_0: 29.99
  • UOPS_PORT_1: 29.4
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 46.57
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 9.01

With loop_count=100 and unroll_count=10

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     a:	48 31 c0             	xor    rax,rax
     d:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
    14:	02 
    15:	48 31 c0             	xor    rax,rax
    18:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    1f:	04 
    20:	48 31 c0             	xor    rax,rax
    23:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    2a:	06 
    2b:	48 31 c0             	xor    rax,rax
    2e:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x8],r8w
    35:	08 
    36:	48 31 c0             	xor    rax,rax
    39:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xa],r8w
    40:	0a 
    41:	48 31 c0             	xor    rax,rax
    44:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xc],r8w
    4b:	0c 
    4c:	48 31 c0             	xor    rax,rax
    4f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xe],r8w
    56:	0e 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 199.41
  • Reference cycles: 220.03
  • UOPS_EXECUTED.THREAD: 72.1
  • RETIRE_SLOTS: 80.1
  • UOPS_MITE: 8.1
  • UOPS_MS: 72.05
  • UOPS_PORT_0: 30.67
  • UOPS_PORT_1: 29.37
  • UOPS_PORT_2: 8.0
  • UOPS_PORT_3: 8.0
  • UOPS_PORT_4: 8.0
  • UOPS_PORT_5: 46.7
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.11

With unroll_count=100 and no inner loop

• Code:

     0:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     7:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
     e:	02 
     f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    16:	04 
    17:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    1e:	06 
    1f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x8],r8w
    26:	08 
    27:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xa],r8w
    2e:	0a 
    2f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xc],r8w
    36:	0c 
    37:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xe],r8w
    3e:	0e 
    3f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x10],r8w
    46:	10 
    47:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x12],r8w
    4e:	12 
    4f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x14],r8w
    56:	14 
    57:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x16],r8w
    5e:	16 
    5f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x18],r8w
    66:	18 
    67:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1a],r8w
    6e:	1a 
    6f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1c],r8w
    76:	1c 
    77:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1e],r8w
    7e:	1e 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 16.0
  • Core cycles: 399.99
  • Reference cycles: 441.28
  • UOPS_EXECUTED.THREAD: 144.0
  • RETIRE_SLOTS: 144.0
  • UOPS_MITE: 0.0
  • UOPS_MS: 144.0
  • UOPS_PORT_0: 37.03
  • UOPS_PORT_1: 34.74
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 69.98
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     7:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
     e:	02 
     f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    16:	04 
    17:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    1e:	06 
    1f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x8],r8w
    26:	08 
    27:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xa],r8w
    2e:	0a 
    2f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xc],r8w
    36:	0c 
    37:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xe],r8w
    3e:	0e 
    3f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x10],r8w
    46:	10 
    47:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x12],r8w
    4e:	12 
    4f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x14],r8w
    56:	14 
    57:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x16],r8w
    5e:	16 
    5f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x18],r8w
    66:	18 
    67:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1a],r8w
    6e:	1a 
    6f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1c],r8w
    76:	1c 
    77:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1e],r8w
    7e:	1e 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 18.0
  • Core cycles: 394.01
  • Reference cycles: 434.76
  • UOPS_EXECUTED.THREAD: 145.0
  • RETIRE_SLOTS: 145.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 144.06
  • UOPS_PORT_0: 35.47
  • UOPS_PORT_1: 34.23
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 69.95
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=10

• Code:

     0:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     7:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
     e:	02 
     f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    16:	04 
    17:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    1e:	06 
    1f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x8],r8w
    26:	08 
    27:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xa],r8w
    2e:	0a 
    2f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xc],r8w
    36:	0c 
    37:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xe],r8w
    3e:	0e 
    3f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x10],r8w
    46:	10 
    47:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x12],r8w
    4e:	12 
    4f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x14],r8w
    56:	14 
    57:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x16],r8w
    5e:	16 
    5f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x18],r8w
    66:	18 
    67:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1a],r8w
    6e:	1a 
    6f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1c],r8w
    76:	1c 
    77:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1e],r8w
    7e:	1e 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 16.2
  • Core cycles: 399.41
  • Reference cycles: 387.31
  • UOPS_EXECUTED.THREAD: 144.1
  • RETIRE_SLOTS: 144.1
  • UOPS_MITE: 0.1
  • UOPS_MS: 144.06
  • UOPS_PORT_0: 36.64
  • UOPS_PORT_1: 34.79
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 70.14
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.1

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     a:	48 31 c0             	xor    rax,rax
     d:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
    14:	02 
    15:	48 31 c0             	xor    rax,rax
    18:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    1f:	04 
    20:	48 31 c0             	xor    rax,rax
    23:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    2a:	06 
    2b:	48 31 c0             	xor    rax,rax
    2e:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x8],r8w
    35:	08 
    36:	48 31 c0             	xor    rax,rax
    39:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xa],r8w
    40:	0a 
    41:	48 31 c0             	xor    rax,rax
    44:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xc],r8w
    4b:	0c 
    4c:	48 31 c0             	xor    rax,rax
    4f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xe],r8w
    56:	0e 
    57:	48 31 c0             	xor    rax,rax
    5a:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x10],r8w
    61:	10 
    62:	48 31 c0             	xor    rax,rax
    65:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x12],r8w
    6c:	12 
    6d:	48 31 c0             	xor    rax,rax
    70:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x14],r8w
    77:	14 
    78:	48 31 c0             	xor    rax,rax
    7b:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x16],r8w
    82:	16 
    83:	48 31 c0             	xor    rax,rax
    86:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x18],r8w
    8d:	18 
    8e:	48 31 c0             	xor    rax,rax
    91:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1a],r8w
    98:	1a 
    99:	48 31 c0             	xor    rax,rax
    9c:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1c],r8w
    a3:	1c 
    a4:	48 31 c0             	xor    rax,rax
    a7:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1e],r8w
    ae:	1e 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 32.0
  • Core cycles: 399.99
  • Reference cycles: 387.89
  • UOPS_EXECUTED.THREAD: 144.0
  • RETIRE_SLOTS: 160.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 144.0
  • UOPS_PORT_0: 46.19
  • UOPS_PORT_1: 43.92
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 87.07
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     a:	48 31 c0             	xor    rax,rax
     d:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
    14:	02 
    15:	48 31 c0             	xor    rax,rax
    18:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    1f:	04 
    20:	48 31 c0             	xor    rax,rax
    23:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    2a:	06 
    2b:	48 31 c0             	xor    rax,rax
    2e:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x8],r8w
    35:	08 
    36:	48 31 c0             	xor    rax,rax
    39:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xa],r8w
    40:	0a 
    41:	48 31 c0             	xor    rax,rax
    44:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xc],r8w
    4b:	0c 
    4c:	48 31 c0             	xor    rax,rax
    4f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xe],r8w
    56:	0e 
    57:	48 31 c0             	xor    rax,rax
    5a:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x10],r8w
    61:	10 
    62:	48 31 c0             	xor    rax,rax
    65:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x12],r8w
    6c:	12 
    6d:	48 31 c0             	xor    rax,rax
    70:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x14],r8w
    77:	14 
    78:	48 31 c0             	xor    rax,rax
    7b:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x16],r8w
    82:	16 
    83:	48 31 c0             	xor    rax,rax
    86:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x18],r8w
    8d:	18 
    8e:	48 31 c0             	xor    rax,rax
    91:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1a],r8w
    98:	1a 
    99:	48 31 c0             	xor    rax,rax
    9c:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1c],r8w
    a3:	1c 
    a4:	48 31 c0             	xor    rax,rax
    a7:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1e],r8w
    ae:	1e 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 34.0
  • Core cycles: 394.01
  • Reference cycles: 382.08
  • UOPS_EXECUTED.THREAD: 145.0
  • RETIRE_SLOTS: 161.0
  • UOPS_MITE: 17.01
  • UOPS_MS: 144.05
  • UOPS_PORT_0: 46.95
  • UOPS_PORT_1: 45.71
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 80.31
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 17.01

With loop_count=100 and unroll_count=10

• Code:

     0:	48 31 c0             	xor    rax,rax
     3:	66 f0 47 0f b1 04 2e 	lock cmpxchg WORD PTR [r14+r13*1],r8w
     a:	48 31 c0             	xor    rax,rax
     d:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x2],r8w
    14:	02 
    15:	48 31 c0             	xor    rax,rax
    18:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x4],r8w
    1f:	04 
    20:	48 31 c0             	xor    rax,rax
    23:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x6],r8w
    2a:	06 
    2b:	48 31 c0             	xor    rax,rax
    2e:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x8],r8w
    35:	08 
    36:	48 31 c0             	xor    rax,rax
    39:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xa],r8w
    40:	0a 
    41:	48 31 c0             	xor    rax,rax
    44:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xc],r8w
    4b:	0c 
    4c:	48 31 c0             	xor    rax,rax
    4f:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0xe],r8w
    56:	0e 
    57:	48 31 c0             	xor    rax,rax
    5a:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x10],r8w
    61:	10 
    62:	48 31 c0             	xor    rax,rax
    65:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x12],r8w
    6c:	12 
    6d:	48 31 c0             	xor    rax,rax
    70:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x14],r8w
    77:	14 
    78:	48 31 c0             	xor    rax,rax
    7b:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x16],r8w
    82:	16 
    83:	48 31 c0             	xor    rax,rax
    86:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x18],r8w
    8d:	18 
    8e:	48 31 c0             	xor    rax,rax
    91:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1a],r8w
    98:	1a 
    99:	48 31 c0             	xor    rax,rax
    9c:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1c],r8w
    a3:	1c 
    a4:	48 31 c0             	xor    rax,rax
    a7:	66 f0 47 0f b1 44 2e 	lock cmpxchg WORD PTR [r14+r13*1+0x1e],r8w
    ae:	1e 
  

• Init:

  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 32.2
  • Core cycles: 399.41
  • Reference cycles: 387.3
  • UOPS_EXECUTED.THREAD: 144.1
  • RETIRE_SLOTS: 160.1
  • UOPS_MITE: 16.11
  • UOPS_MS: 144.05
  • UOPS_PORT_0: 47.71
  • UOPS_PORT_1: 46.21
  • UOPS_PORT_2: 16.0
  • UOPS_PORT_3: 16.0
  • UOPS_PORT_4: 16.0
  • UOPS_PORT_5: 80.47
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 16.11