XCHG (R64, R64) - Throughput and Uops (IACA 2.3)

With different registers for different operands

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 0.00 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 0.0  | 0.0    0.0  | 0.0    0.0  | 0.0  | 0.0  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   0    |           |     |           |           |     |     |    | xchg r8, r9
Total Num Of Uops: 0

With 6 independent instructions

Throughput Analysis Report
--------------------------
Block Throughput: 0.00 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 0.0  | 0.0    0.0  | 0.0    0.0  | 0.0  | 0.0  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   0    |           |     |           |           |     |     |    | xchg r8, r9
|   0    |           |     |           |           |     |     |    | xchg r10, r11
|   0    |           |     |           |           |     |     |    | xchg r12, r13
|   0    |           |     |           |           |     |     |    | xchg r14, rbx
|   0    |           |     |           |           |     |     |    | xchg rcx, rdx
|   0    |           |     |           |           |     |     |    | xchg rdi, rsi
Total Num Of Uops: 0

With the same register for for different operands

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 0.00 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 0.0  | 0.0    0.0  | 0.0    0.0  | 0.0  | 0.0  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   0    |           |     |           |           |     |     |    | xchg r8, r8
Total Num Of Uops: 0

With 13 independent instructions

Throughput Analysis Report
--------------------------
Block Throughput: 0.00 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 0.0  | 0.0    0.0  | 0.0    0.0  | 0.0  | 0.0  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   0    |           |     |           |           |     |     |    | xchg r8, r8
|   0    |           |     |           |           |     |     |    | xchg r9, r9
|   0    |           |     |           |           |     |     |    | xchg r10, r10
|   0    |           |     |           |           |     |     |    | xchg r11, r11
|   0    |           |     |           |           |     |     |    | xchg r12, r12
|   0    |           |     |           |           |     |     |    | xchg r13, r13
|   0    |           |     |           |           |     |     |    | xchg r14, r14
|   0    |           |     |           |           |     |     |    | xchg rbx, rbx
|   0    |           |     |           |           |     |     |    | xchg rcx, rcx
|   0    |           |     |           |           |     |     |    | xchg rdx, rdx
|   0    |           |     |           |           |     |     |    | xchg rdi, rdi
|   0    |           |     |           |           |     |     |    | xchg rsi, rsi
|   0    |           |     |           |           |     |     |    | xchg rbp, rbp
Total Num Of Uops: 0