ROR (R32, I8) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 1.0
  • Reference cycles: 0.89
  • UOPS_EXECUTED.THREAD: 1.0
  • RETIRE_SLOTS: 1.0
  • UOPS_MITE: 1.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.5
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.5
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 1.0
  • Reference cycles: 0.89
  • UOPS_EXECUTED.THREAD: 1.1
  • RETIRE_SLOTS: 1.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.51
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.59
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 1.0
  • Reference cycles: 0.88
  • UOPS_EXECUTED.THREAD: 1.01
  • RETIRE_SLOTS: 1.01
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.5
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.51
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With unroll_count=200 and no inner loop

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	41 c1 c9 02          	ror    r9d,0x2
     8:	41 c1 ca 02          	ror    r10d,0x2
     c:	41 c1 cb 02          	ror    r11d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 2.0
  • Reference cycles: 1.88
  • UOPS_EXECUTED.THREAD: 4.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 2.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	41 c1 c9 02          	ror    r9d,0x2
     8:	41 c1 ca 02          	ror    r10d,0x2
     c:	41 c1 cb 02          	ror    r11d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 2.26
  • Reference cycles: 2.0
  • UOPS_EXECUTED.THREAD: 4.51
  • RETIRE_SLOTS: 4.5
  • UOPS_MITE: 0.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.25
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 2.25
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=20

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	41 c1 c9 02          	ror    r9d,0x2
     8:	41 c1 ca 02          	ror    r10d,0x2
     c:	41 c1 cb 02          	ror    r11d,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 2.04
  • Reference cycles: 1.8
  • UOPS_EXECUTED.THREAD: 4.06
  • RETIRE_SLOTS: 4.05
  • UOPS_MITE: 0.04
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 2.03
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 2.03
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=100 and no inner loop

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	41 c1 c9 02          	ror    r9d,0x2
     8:	41 c1 ca 02          	ror    r10d,0x2
     c:	41 c1 cb 02          	ror    r11d,0x2
    10:	41 c1 cc 02          	ror    r12d,0x2
    14:	41 c1 cd 02          	ror    r13d,0x2
    18:	41 c1 ce 02          	ror    r14d,0x2
    1c:	c1 cb 02             	ror    ebx,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 4.0
  • Reference cycles: 3.33
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.0
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 4.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	41 c1 c9 02          	ror    r9d,0x2
     8:	41 c1 ca 02          	ror    r10d,0x2
     c:	41 c1 cb 02          	ror    r11d,0x2
    10:	41 c1 cc 02          	ror    r12d,0x2
    14:	41 c1 cd 02          	ror    r13d,0x2
    18:	41 c1 ce 02          	ror    r14d,0x2
    1c:	c1 cb 02             	ror    ebx,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 4.53
  • Reference cycles: 3.99
  • UOPS_EXECUTED.THREAD: 9.01
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 9.11
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.51
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 4.51
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 3.04

With loop_count=100 and unroll_count=10

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	41 c1 c9 02          	ror    r9d,0x2
     8:	41 c1 ca 02          	ror    r10d,0x2
     c:	41 c1 cb 02          	ror    r11d,0x2
    10:	41 c1 cc 02          	ror    r12d,0x2
    14:	41 c1 cd 02          	ror    r13d,0x2
    18:	41 c1 ce 02          	ror    r14d,0x2
    1c:	c1 cb 02             	ror    ebx,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 4.07
  • Reference cycles: 3.59
  • UOPS_EXECUTED.THREAD: 8.11
  • RETIRE_SLOTS: 8.1
  • UOPS_MITE: 0.08
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 4.06
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 4.06
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.02

With unroll_count=100 and no inner loop

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	41 c1 c9 02          	ror    r9d,0x2
     8:	41 c1 ca 02          	ror    r10d,0x2
     c:	41 c1 cb 02          	ror    r11d,0x2
    10:	41 c1 cc 02          	ror    r12d,0x2
    14:	41 c1 cd 02          	ror    r13d,0x2
    18:	41 c1 ce 02          	ror    r14d,0x2
    1c:	c1 cb 02             	ror    ebx,0x2
    1f:	c1 c9 02             	ror    ecx,0x2
    22:	c1 ca 02             	ror    edx,0x2
    25:	c1 cf 02             	ror    edi,0x2
    28:	c1 ce 02             	ror    esi,0x2
    2b:	c1 cd 02             	ror    ebp,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 13.0
  • Core cycles: 6.5
  • Reference cycles: 5.99
  • UOPS_EXECUTED.THREAD: 13.0
  • RETIRE_SLOTS: 13.0
  • UOPS_MITE: 13.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 6.5
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 6.5
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 3.25

With loop_count=1000 and unroll_count=1

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	41 c1 c9 02          	ror    r9d,0x2
     8:	41 c1 ca 02          	ror    r10d,0x2
     c:	41 c1 cb 02          	ror    r11d,0x2
    10:	41 c1 cc 02          	ror    r12d,0x2
    14:	41 c1 cd 02          	ror    r13d,0x2
    18:	41 c1 ce 02          	ror    r14d,0x2
    1c:	c1 cb 02             	ror    ebx,0x2
    1f:	c1 c9 02             	ror    ecx,0x2
    22:	c1 ca 02             	ror    edx,0x2
    25:	c1 cf 02             	ror    edi,0x2
    28:	c1 ce 02             	ror    esi,0x2
    2b:	c1 cd 02             	ror    ebp,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 15.0
  • Core cycles: 7.02
  • Reference cycles: 6.3
  • UOPS_EXECUTED.THREAD: 14.01
  • RETIRE_SLOTS: 14.0
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 7.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 7.01
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	41 c1 c9 02          	ror    r9d,0x2
     8:	41 c1 ca 02          	ror    r10d,0x2
     c:	41 c1 cb 02          	ror    r11d,0x2
    10:	41 c1 cc 02          	ror    r12d,0x2
    14:	41 c1 cd 02          	ror    r13d,0x2
    18:	41 c1 ce 02          	ror    r14d,0x2
    1c:	c1 cb 02             	ror    ebx,0x2
    1f:	c1 c9 02             	ror    ecx,0x2
    22:	c1 ca 02             	ror    edx,0x2
    25:	c1 cf 02             	ror    edi,0x2
    28:	c1 ce 02             	ror    esi,0x2
    2b:	c1 cd 02             	ror    ebp,0x2
  

• Show nanoBench command
• Results:
  • Instructions retired: 13.2
  • Core cycles: 6.58
  • Reference cycles: 5.85
  • UOPS_EXECUTED.THREAD: 13.11
  • RETIRE_SLOTS: 13.1
  • UOPS_MITE: 0.13
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 6.56
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 6.56
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.03

With JB (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 82 00 00 00 00    	jb     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.07
  • Reference cycles: 1.33
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JB (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	72 00                	jb     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.07
  • Reference cycles: 0.89
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JBE (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 86 00 00 00 00    	jbe    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.08
  • Reference cycles: 0.89
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JBE (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	76 00                	jbe    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.08
  • Reference cycles: 0.67
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JL (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 8c 00 00 00 00    	jl     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.05
  • Reference cycles: 0.89
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JL (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	7c 00                	jl     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 1.11
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JLE (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 8e 00 00 00 00    	jle    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 0.67
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JLE (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	7e 00                	jle    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 0.67
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JNB (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 83 00 00 00 00    	jae    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.23
  • Reference cycles: 0.89
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.41
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.99
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.01
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.74

With JNB (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	73 00                	jae    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.19
  • Reference cycles: 0.67
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.72
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.99
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.0
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.89

With JNBE (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 87 00 00 00 00    	ja     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.32
  • Reference cycles: 1.33
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.4
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.98
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.02
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.76

With JNBE (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	77 00                	ja     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.31
  • Reference cycles: 1.33
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.75
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.99
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.01
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.89

With JNL (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 8d 00 00 00 00    	jge    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.34
  • Reference cycles: 1.33
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.1
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.88
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.12
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.69

With JNL (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	7d 00                	jge    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.21
  • Reference cycles: 1.55
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.57
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.9
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.11
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.66

With JNLE (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 8f 00 00 00 00    	jg     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.23
  • Reference cycles: 0.44
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.03
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.9
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.07
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.59

With JNLE (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	7f 00                	jg     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.22
  • Reference cycles: 1.33
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.36
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.92
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.1
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.76

With JNO (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 81 00 00 00 00    	jno    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.18
  • Reference cycles: 0.67
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.31
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.96
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.05
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.74

With JNO (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	71 00                	jno    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.21
  • Reference cycles: 0.44
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.68
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.95
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.04
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.94

With JNP (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 8b 00 00 00 00    	jnp    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.78
  • Reference cycles: 1.55
  • UOPS_EXECUTED.THREAD: 2.05
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.88
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.96
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.09
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.8

With JNP (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	7b 00                	jnp    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.93
  • Reference cycles: 1.77
  • UOPS_EXECUTED.THREAD: 2.05
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.89
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.96
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.08
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.75

With JNS (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 89 00 00 00 00    	jns    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.54
  • Reference cycles: 1.55
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 0.9
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.9
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.08
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.68

With JNS (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	79 00                	jns    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.18
  • Reference cycles: 0.89
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.52
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.9
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.08
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.78

With JNZ (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 85 00 00 00 00    	jne    0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.21
  • Reference cycles: 0.89
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.44
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.97
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.06
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.74

With JNZ (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	75 00                	jne    0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.61
  • Reference cycles: 1.33
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.76
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.97
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.03
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.97

With JO (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 80 00 00 00 00    	jo     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 1.11
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JO (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	70 00                	jo     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 0.44
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JP (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 8a 00 00 00 00    	jp     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.68
  • Reference cycles: 1.77
  • UOPS_EXECUTED.THREAD: 2.06
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.73
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.98
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.12
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.82

With JP (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	7a 00                	jp     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 2.02
  • Reference cycles: 1.55
  • UOPS_EXECUTED.THREAD: 2.06
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 1.77
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 0.93
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 1.13
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.75

With JS (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 88 00 00 00 00    	js     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 0.89
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JS (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	78 00                	js     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 0.44
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JZ (Rel32)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	0f 84 00 00 00 00    	je     0xa
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 1.11
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.0
  • UOPS_PORT_1: 0.01
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57

With JZ (Rel8)

• Code:

     0:	41 c1 c8 02          	ror    r8d,0x2
     4:	74 00                	je     0x6
  

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.06
  • Reference cycles: 0.67
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_PORT_0: 1.01
  • UOPS_PORT_1: 0.0
  • UOPS_PORT_2: 0.0
  • UOPS_PORT_3: 0.0
  • UOPS_PORT_4: 0.0
  • UOPS_PORT_5: 0.0
  • UOPS_PORT_6: 0.99
  • UOPS_PORT_7: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.57