VBROADCASTI64X2 (ZMM, K, M128)

With unroll_count=500 and no inner loop

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.12
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.95
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 1.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.3

With loop_count=1000, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   d:	0f 1f 84 00 00 00 00 
  14:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 1.0
- Reference cycles: 0.95
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.94
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100, unroll_count=100, and padding (long NOPs)

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   d:	0f 1f 84 00 00 00 00 
  14:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 1.0
- Reference cycles: 0.95
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	62 d2 fd 49 5a 4e 01 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+0x10]
   d:	62 d2 fd 49 5a 56 02 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+0x20]
  14:	62 d2 fd 49 5a 5e 03 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+0x30]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.95
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	62 d2 fd 49 5a 4e 01 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+0x10]
   d:	62 d2 fd 49 5a 56 02 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+0x20]
  14:	62 d2 fd 49 5a 5e 03 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+0x30]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.01
- Reference cycles: 1.89
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=2, and padding (long NOPs)

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	62 d2 fd 49 5a 4e 01 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+0x10]
   d:	62 d2 fd 49 5a 56 02 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+0x20]
  14:	62 d2 fd 49 5a 5e 03 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+0x30]
  1b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  22:	0f 1f 84 00 00 00 00 
  29:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 2.01
- Reference cycles: 1.9
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 5.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	62 d2 fd 49 5a 4e 01 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+0x10]
   d:	62 d2 fd 49 5a 56 02 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+0x20]
  14:	62 d2 fd 49 5a 5e 03 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+0x30]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.01
- Reference cycles: 2.03
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.29
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.11

With loop_count=100, unroll_count=20, and padding (long NOPs)

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	62 d2 fd 49 5a 4e 01 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+0x10]
   d:	62 d2 fd 49 5a 56 02 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+0x20]
  14:	62 d2 fd 49 5a 5e 03 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+0x30]
  1b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  22:	0f 1f 84 00 00 00 00 
  29:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 5.1
- Core cycles: 2.01
- Reference cycles: 1.9
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 5.05
- UOPS_MITE: 0.05
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	62 d2 fd 49 5a 4e 01 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+0x10]
   d:	62 d2 fd 49 5a 56 02 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+0x20]
  14:	62 d2 fd 49 5a 5e 03 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+0x30]
  1b:	62 d2 fd 49 5a 66 04 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+0x40]
  22:	62 d2 fd 49 5a 6e 05 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+0x50]
  29:	62 d2 fd 49 5a 76 06 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+0x60]
  30:	62 d2 fd 49 5a 7e 07 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+0x70]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 4.14
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	62 d2 fd 49 5a 4e 01 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+0x10]
   d:	62 d2 fd 49 5a 56 02 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+0x20]
  14:	62 d2 fd 49 5a 5e 03 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+0x30]
  1b:	62 d2 fd 49 5a 66 04 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+0x40]
  22:	62 d2 fd 49 5a 6e 05 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+0x50]
  29:	62 d2 fd 49 5a 76 06 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+0x60]
  30:	62 d2 fd 49 5a 7e 07 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+0x70]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.02
- Reference cycles: 3.8
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 9.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	62 d2 fd 49 5a 4e 01 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+0x10]
   d:	62 d2 fd 49 5a 56 02 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+0x20]
  14:	62 d2 fd 49 5a 5e 03 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+0x30]
  1b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  22:	0f 1f 84 00 00 00 00 
  29:	00 
  2a:	62 d2 fd 49 5a 66 04 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+0x40]
  31:	62 d2 fd 49 5a 6e 05 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+0x50]
  38:	62 d2 fd 49 5a 76 06 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+0x60]
  3f:	62 d2 fd 49 5a 7e 07 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+0x70]
  46:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  4d:	0f 1f 84 00 00 00 00 
  54:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 4.02
- Reference cycles: 3.8
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 11.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	62 d2 fd 49 5a 4e 01 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+0x10]
   d:	62 d2 fd 49 5a 56 02 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+0x20]
  14:	62 d2 fd 49 5a 5e 03 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+0x30]
  1b:	62 d2 fd 49 5a 66 04 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+0x40]
  22:	62 d2 fd 49 5a 6e 05 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+0x50]
  29:	62 d2 fd 49 5a 76 06 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+0x60]
  30:	62 d2 fd 49 5a 7e 07 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+0x70]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.02
- Reference cycles: 3.72
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	62 d2 fd 49 5a 4e 01 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+0x10]
   d:	62 d2 fd 49 5a 56 02 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+0x20]
  14:	62 d2 fd 49 5a 5e 03 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+0x30]
  1b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  22:	0f 1f 84 00 00 00 00 
  29:	00 
  2a:	62 d2 fd 49 5a 66 04 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+0x40]
  31:	62 d2 fd 49 5a 6e 05 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+0x50]
  38:	62 d2 fd 49 5a 76 06 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+0x60]
  3f:	62 d2 fd 49 5a 7e 07 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+0x70]
  46:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  4d:	0f 1f 84 00 00 00 00 
  54:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 10.2
- Core cycles: 4.02
- Reference cycles: 3.8
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 10.1
- UOPS_MITE: 0.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	62 d2 fd 49 5a 4e 01 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+0x10]
   d:	62 d2 fd 49 5a 56 02 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+0x20]
  14:	62 d2 fd 49 5a 5e 03 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+0x30]
  1b:	62 d2 fd 49 5a 66 04 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+0x40]
  22:	62 d2 fd 49 5a 6e 05 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+0x50]
  29:	62 d2 fd 49 5a 76 06 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+0x60]
  30:	62 d2 fd 49 5a 7e 07 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+0x70]
  37:	62 52 fd 49 5a 46 08 	vbroadcasti64x2 zmm8{k1},XMMWORD PTR [r14+0x80]
  3e:	62 52 fd 49 5a 4e 09 	vbroadcasti64x2 zmm9{k1},XMMWORD PTR [r14+0x90]
  45:	62 52 fd 49 5a 56 0a 	vbroadcasti64x2 zmm10{k1},XMMWORD PTR [r14+0xa0]
  4c:	62 52 fd 49 5a 5e 0b 	vbroadcasti64x2 zmm11{k1},XMMWORD PTR [r14+0xb0]
  53:	62 52 fd 49 5a 66 0c 	vbroadcasti64x2 zmm12{k1},XMMWORD PTR [r14+0xc0]
  5a:	62 c2 fd 49 5a 46 0d 	vbroadcasti64x2 zmm16{k1},XMMWORD PTR [r14+0xd0]
  61:	62 c2 fd 49 5a 4e 0e 	vbroadcasti64x2 zmm17{k1},XMMWORD PTR [r14+0xe0]
  68:	62 c2 fd 49 5a 56 0f 	vbroadcasti64x2 zmm18{k1},XMMWORD PTR [r14+0xf0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 8.0
- Reference cycles: 6.57
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	62 d2 fd 49 5a 4e 01 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+0x10]
   d:	62 d2 fd 49 5a 56 02 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+0x20]
  14:	62 d2 fd 49 5a 5e 03 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+0x30]
  1b:	62 d2 fd 49 5a 66 04 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+0x40]
  22:	62 d2 fd 49 5a 6e 05 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+0x50]
  29:	62 d2 fd 49 5a 76 06 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+0x60]
  30:	62 d2 fd 49 5a 7e 07 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+0x70]
  37:	62 52 fd 49 5a 46 08 	vbroadcasti64x2 zmm8{k1},XMMWORD PTR [r14+0x80]
  3e:	62 52 fd 49 5a 4e 09 	vbroadcasti64x2 zmm9{k1},XMMWORD PTR [r14+0x90]
  45:	62 52 fd 49 5a 56 0a 	vbroadcasti64x2 zmm10{k1},XMMWORD PTR [r14+0xa0]
  4c:	62 52 fd 49 5a 5e 0b 	vbroadcasti64x2 zmm11{k1},XMMWORD PTR [r14+0xb0]
  53:	62 52 fd 49 5a 66 0c 	vbroadcasti64x2 zmm12{k1},XMMWORD PTR [r14+0xc0]
  5a:	62 c2 fd 49 5a 46 0d 	vbroadcasti64x2 zmm16{k1},XMMWORD PTR [r14+0xd0]
  61:	62 c2 fd 49 5a 4e 0e 	vbroadcasti64x2 zmm17{k1},XMMWORD PTR [r14+0xe0]
  68:	62 c2 fd 49 5a 56 0f 	vbroadcasti64x2 zmm18{k1},XMMWORD PTR [r14+0xf0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.02
- Reference cycles: 7.59
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	62 d2 fd 49 5a 4e 01 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+0x10]
   d:	62 d2 fd 49 5a 56 02 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+0x20]
  14:	62 d2 fd 49 5a 5e 03 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+0x30]
  1b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  22:	0f 1f 84 00 00 00 00 
  29:	00 
  2a:	62 d2 fd 49 5a 66 04 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+0x40]
  31:	62 d2 fd 49 5a 6e 05 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+0x50]
  38:	62 d2 fd 49 5a 76 06 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+0x60]
  3f:	62 d2 fd 49 5a 7e 07 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+0x70]
  46:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  4d:	0f 1f 84 00 00 00 00 
  54:	00 
  55:	62 52 fd 49 5a 46 08 	vbroadcasti64x2 zmm8{k1},XMMWORD PTR [r14+0x80]
  5c:	62 52 fd 49 5a 4e 09 	vbroadcasti64x2 zmm9{k1},XMMWORD PTR [r14+0x90]
  63:	62 52 fd 49 5a 56 0a 	vbroadcasti64x2 zmm10{k1},XMMWORD PTR [r14+0xa0]
  6a:	62 52 fd 49 5a 5e 0b 	vbroadcasti64x2 zmm11{k1},XMMWORD PTR [r14+0xb0]
  71:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  78:	0f 1f 84 00 00 00 00 
  7f:	00 
  80:	62 52 fd 49 5a 66 0c 	vbroadcasti64x2 zmm12{k1},XMMWORD PTR [r14+0xc0]
  87:	62 c2 fd 49 5a 46 0d 	vbroadcasti64x2 zmm16{k1},XMMWORD PTR [r14+0xd0]
  8e:	62 c2 fd 49 5a 4e 0e 	vbroadcasti64x2 zmm17{k1},XMMWORD PTR [r14+0xe0]
  95:	62 c2 fd 49 5a 56 0f 	vbroadcasti64x2 zmm18{k1},XMMWORD PTR [r14+0xf0]
  9c:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  a3:	0f 1f 84 00 00 00 00 
  aa:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 22.0
- Core cycles: 8.02
- Reference cycles: 7.59
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 21.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	62 d2 fd 49 5a 4e 01 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+0x10]
   d:	62 d2 fd 49 5a 56 02 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+0x20]
  14:	62 d2 fd 49 5a 5e 03 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+0x30]
  1b:	62 d2 fd 49 5a 66 04 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+0x40]
  22:	62 d2 fd 49 5a 6e 05 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+0x50]
  29:	62 d2 fd 49 5a 76 06 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+0x60]
  30:	62 d2 fd 49 5a 7e 07 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+0x70]
  37:	62 52 fd 49 5a 46 08 	vbroadcasti64x2 zmm8{k1},XMMWORD PTR [r14+0x80]
  3e:	62 52 fd 49 5a 4e 09 	vbroadcasti64x2 zmm9{k1},XMMWORD PTR [r14+0x90]
  45:	62 52 fd 49 5a 56 0a 	vbroadcasti64x2 zmm10{k1},XMMWORD PTR [r14+0xa0]
  4c:	62 52 fd 49 5a 5e 0b 	vbroadcasti64x2 zmm11{k1},XMMWORD PTR [r14+0xb0]
  53:	62 52 fd 49 5a 66 0c 	vbroadcasti64x2 zmm12{k1},XMMWORD PTR [r14+0xc0]
  5a:	62 c2 fd 49 5a 46 0d 	vbroadcasti64x2 zmm16{k1},XMMWORD PTR [r14+0xd0]
  61:	62 c2 fd 49 5a 4e 0e 	vbroadcasti64x2 zmm17{k1},XMMWORD PTR [r14+0xe0]
  68:	62 c2 fd 49 5a 56 0f 	vbroadcasti64x2 zmm18{k1},XMMWORD PTR [r14+0xf0]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.02
- Reference cycles: 7.57
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.11
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 d2 fd 49 5a 06    	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14]
   6:	62 d2 fd 49 5a 4e 01 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+0x10]
   d:	62 d2 fd 49 5a 56 02 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+0x20]
  14:	62 d2 fd 49 5a 5e 03 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+0x30]
  1b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  22:	0f 1f 84 00 00 00 00 
  29:	00 
  2a:	62 d2 fd 49 5a 66 04 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+0x40]
  31:	62 d2 fd 49 5a 6e 05 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+0x50]
  38:	62 d2 fd 49 5a 76 06 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+0x60]
  3f:	62 d2 fd 49 5a 7e 07 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+0x70]
  46:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  4d:	0f 1f 84 00 00 00 00 
  54:	00 
  55:	62 52 fd 49 5a 46 08 	vbroadcasti64x2 zmm8{k1},XMMWORD PTR [r14+0x80]
  5c:	62 52 fd 49 5a 4e 09 	vbroadcasti64x2 zmm9{k1},XMMWORD PTR [r14+0x90]
  63:	62 52 fd 49 5a 56 0a 	vbroadcasti64x2 zmm10{k1},XMMWORD PTR [r14+0xa0]
  6a:	62 52 fd 49 5a 5e 0b 	vbroadcasti64x2 zmm11{k1},XMMWORD PTR [r14+0xb0]
  71:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  78:	0f 1f 84 00 00 00 00 
  7f:	00 
  80:	62 52 fd 49 5a 66 0c 	vbroadcasti64x2 zmm12{k1},XMMWORD PTR [r14+0xc0]
  87:	62 c2 fd 49 5a 46 0d 	vbroadcasti64x2 zmm16{k1},XMMWORD PTR [r14+0xd0]
  8e:	62 c2 fd 49 5a 4e 0e 	vbroadcasti64x2 zmm17{k1},XMMWORD PTR [r14+0xe0]
  95:	62 c2 fd 49 5a 56 0f 	vbroadcasti64x2 zmm18{k1},XMMWORD PTR [r14+0xf0]
  9c:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  a3:	0f 1f 84 00 00 00 00 
  aa:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 20.2
- Core cycles: 8.02
- Reference cycles: 7.62
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 20.1
- UOPS_MITE: 0.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.92
- UOPS_EXECUTED.THREAD: 2.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.94
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   e:	0f 1f 84 00 00 00 00 
  15:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 1.0
- Reference cycles: 0.95
- UOPS_EXECUTED.THREAD: 2.1
- RETIRE_SLOTS: 2.1
- UOPS_MITE: 0.3
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.1

With loop_count=100 and unroll_count=100

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.95
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With loop_count=100, unroll_count=100, and padding (long NOPs)

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   e:	0f 1f 84 00 00 00 00 
  15:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 1.0
- Reference cycles: 0.94
- UOPS_EXECUTED.THREAD: 2.01
- RETIRE_SLOTS: 2.01
- UOPS_MITE: 0.05
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.5
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	62 92 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+r13*1+0x10]
   e:	01 
   f:	62 92 fd 49 5a 54 2e 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+r13*1+0x20]
  16:	02 
  17:	62 92 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+r13*1+0x30]
  1e:	03

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.7
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	62 92 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+r13*1+0x10]
   e:	01 
   f:	62 92 fd 49 5a 54 2e 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+r13*1+0x20]
  16:	02 
  17:	62 92 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+r13*1+0x30]
  1e:	03

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 2.5
- Reference cycles: 2.34
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 4.51
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.49

With loop_count=1000, unroll_count=2, and padding (long NOPs)

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	62 92 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+r13*1+0x10]
   e:	01 
   f:	62 92 fd 49 5a 54 2e 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+r13*1+0x20]
  16:	02 
  17:	62 92 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+r13*1+0x30]
  1e:	03 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 2.01
- Reference cycles: 1.93
- UOPS_EXECUTED.THREAD: 8.5
- RETIRE_SLOTS: 5.5
- UOPS_MITE: 1.51
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.5

With loop_count=100 and unroll_count=20

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	62 92 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+r13*1+0x10]
   e:	01 
   f:	62 92 fd 49 5a 54 2e 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+r13*1+0x20]
  16:	02 
  17:	62 92 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+r13*1+0x30]
  1e:	03

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 2.01
- Reference cycles: 2.03
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100, unroll_count=20, and padding (long NOPs)

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	62 92 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+r13*1+0x10]
   e:	01 
   f:	62 92 fd 49 5a 54 2e 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+r13*1+0x20]
  16:	02 
  17:	62 92 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+r13*1+0x30]
  1e:	03 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3

Show nanoBench command
Results:
- Instructions retired: 5.1
- Core cycles: 2.01
- Reference cycles: 1.91
- UOPS_EXECUTED.THREAD: 8.05
- RETIRE_SLOTS: 5.05
- UOPS_MITE: 0.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	62 92 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+r13*1+0x10]
   e:	01 
   f:	62 92 fd 49 5a 54 2e 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+r13*1+0x20]
  16:	02 
  17:	62 92 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+r13*1+0x30]
  1e:	03 
  1f:	62 92 fd 49 5a 64 2e 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+r13*1+0x40]
  26:	04 
  27:	62 92 fd 49 5a 6c 2e 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+r13*1+0x50]
  2e:	05 
  2f:	62 92 fd 49 5a 74 2e 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+r13*1+0x60]
  36:	06 
  37:	62 92 fd 49 5a 7c 2e 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+r13*1+0x70]
  3e:	07

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 4.38
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.11

With loop_count=1000 and unroll_count=1

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	62 92 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+r13*1+0x10]
   e:	01 
   f:	62 92 fd 49 5a 54 2e 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+r13*1+0x20]
  16:	02 
  17:	62 92 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+r13*1+0x30]
  1e:	03 
  1f:	62 92 fd 49 5a 64 2e 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+r13*1+0x40]
  26:	04 
  27:	62 92 fd 49 5a 6c 2e 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+r13*1+0x50]
  2e:	05 
  2f:	62 92 fd 49 5a 74 2e 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+r13*1+0x60]
  36:	06 
  37:	62 92 fd 49 5a 7c 2e 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+r13*1+0x70]
  3e:	07

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 4.99
- Reference cycles: 4.82
- UOPS_EXECUTED.THREAD: 17.01
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 9.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.99

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	62 92 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+r13*1+0x10]
   e:	01 
   f:	62 92 fd 49 5a 54 2e 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+r13*1+0x20]
  16:	02 
  17:	62 92 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+r13*1+0x30]
  1e:	03 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00 
  2e:	62 92 fd 49 5a 64 2e 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+r13*1+0x40]
  35:	04 
  36:	62 92 fd 49 5a 6c 2e 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+r13*1+0x50]
  3d:	05 
  3e:	62 92 fd 49 5a 74 2e 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+r13*1+0x60]
  45:	06 
  46:	62 92 fd 49 5a 7c 2e 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+r13*1+0x70]
  4d:	07 
  4e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  55:	0f 1f 84 00 00 00 00 
  5c:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 4.02
- Reference cycles: 3.72
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 11.0
- UOPS_MITE: 3.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	62 92 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+r13*1+0x10]
   e:	01 
   f:	62 92 fd 49 5a 54 2e 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+r13*1+0x20]
  16:	02 
  17:	62 92 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+r13*1+0x30]
  1e:	03 
  1f:	62 92 fd 49 5a 64 2e 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+r13*1+0x40]
  26:	04 
  27:	62 92 fd 49 5a 6c 2e 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+r13*1+0x50]
  2e:	05 
  2f:	62 92 fd 49 5a 74 2e 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+r13*1+0x60]
  36:	06 
  37:	62 92 fd 49 5a 7c 2e 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+r13*1+0x70]
  3e:	07

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 4.02
- Reference cycles: 4.02
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	62 92 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+r13*1+0x10]
   e:	01 
   f:	62 92 fd 49 5a 54 2e 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+r13*1+0x20]
  16:	02 
  17:	62 92 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+r13*1+0x30]
  1e:	03 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00 
  2e:	62 92 fd 49 5a 64 2e 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+r13*1+0x40]
  35:	04 
  36:	62 92 fd 49 5a 6c 2e 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+r13*1+0x50]
  3d:	05 
  3e:	62 92 fd 49 5a 74 2e 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+r13*1+0x60]
  45:	06 
  46:	62 92 fd 49 5a 7c 2e 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+r13*1+0x70]
  4d:	07 
  4e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  55:	0f 1f 84 00 00 00 00 
  5c:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7

Show nanoBench command
Results:
- Instructions retired: 10.2
- Core cycles: 4.02
- Reference cycles: 3.82
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 10.1
- UOPS_MITE: 0.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	62 92 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+r13*1+0x10]
   e:	01 
   f:	62 92 fd 49 5a 54 2e 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+r13*1+0x20]
  16:	02 
  17:	62 92 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+r13*1+0x30]
  1e:	03 
  1f:	62 92 fd 49 5a 64 2e 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+r13*1+0x40]
  26:	04 
  27:	62 92 fd 49 5a 6c 2e 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+r13*1+0x50]
  2e:	05 
  2f:	62 92 fd 49 5a 74 2e 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+r13*1+0x60]
  36:	06 
  37:	62 92 fd 49 5a 7c 2e 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+r13*1+0x70]
  3e:	07 
  3f:	62 12 fd 49 5a 44 2e 	vbroadcasti64x2 zmm8{k1},XMMWORD PTR [r14+r13*1+0x80]
  46:	08 
  47:	62 12 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm9{k1},XMMWORD PTR [r14+r13*1+0x90]
  4e:	09 
  4f:	62 12 fd 49 5a 54 2e 	vbroadcasti64x2 zmm10{k1},XMMWORD PTR [r14+r13*1+0xa0]
  56:	0a 
  57:	62 12 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm11{k1},XMMWORD PTR [r14+r13*1+0xb0]
  5e:	0b 
  5f:	62 12 fd 49 5a 64 2e 	vbroadcasti64x2 zmm12{k1},XMMWORD PTR [r14+r13*1+0xc0]
  66:	0c 
  67:	62 82 fd 49 5a 44 2e 	vbroadcasti64x2 zmm16{k1},XMMWORD PTR [r14+r13*1+0xd0]
  6e:	0d 
  6f:	62 82 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm17{k1},XMMWORD PTR [r14+r13*1+0xe0]
  76:	0e 
  77:	62 82 fd 49 5a 54 2e 	vbroadcasti64x2 zmm18{k1},XMMWORD PTR [r14+r13*1+0xf0]
  7e:	0f

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 8.0
- Reference cycles: 7.79
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.04

With loop_count=1000 and unroll_count=1

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	62 92 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+r13*1+0x10]
   e:	01 
   f:	62 92 fd 49 5a 54 2e 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+r13*1+0x20]
  16:	02 
  17:	62 92 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+r13*1+0x30]
  1e:	03 
  1f:	62 92 fd 49 5a 64 2e 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+r13*1+0x40]
  26:	04 
  27:	62 92 fd 49 5a 6c 2e 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+r13*1+0x50]
  2e:	05 
  2f:	62 92 fd 49 5a 74 2e 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+r13*1+0x60]
  36:	06 
  37:	62 92 fd 49 5a 7c 2e 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+r13*1+0x70]
  3e:	07 
  3f:	62 12 fd 49 5a 44 2e 	vbroadcasti64x2 zmm8{k1},XMMWORD PTR [r14+r13*1+0x80]
  46:	08 
  47:	62 12 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm9{k1},XMMWORD PTR [r14+r13*1+0x90]
  4e:	09 
  4f:	62 12 fd 49 5a 54 2e 	vbroadcasti64x2 zmm10{k1},XMMWORD PTR [r14+r13*1+0xa0]
  56:	0a 
  57:	62 12 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm11{k1},XMMWORD PTR [r14+r13*1+0xb0]
  5e:	0b 
  5f:	62 12 fd 49 5a 64 2e 	vbroadcasti64x2 zmm12{k1},XMMWORD PTR [r14+r13*1+0xc0]
  66:	0c 
  67:	62 82 fd 49 5a 44 2e 	vbroadcasti64x2 zmm16{k1},XMMWORD PTR [r14+r13*1+0xd0]
  6e:	0d 
  6f:	62 82 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm17{k1},XMMWORD PTR [r14+r13*1+0xe0]
  76:	0e 
  77:	62 82 fd 49 5a 54 2e 	vbroadcasti64x2 zmm18{k1},XMMWORD PTR [r14+r13*1+0xf0]
  7e:	0f

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.02
- Reference cycles: 8.3
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 8.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.01

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	62 92 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+r13*1+0x10]
   e:	01 
   f:	62 92 fd 49 5a 54 2e 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+r13*1+0x20]
  16:	02 
  17:	62 92 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+r13*1+0x30]
  1e:	03 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00 
  2e:	62 92 fd 49 5a 64 2e 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+r13*1+0x40]
  35:	04 
  36:	62 92 fd 49 5a 6c 2e 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+r13*1+0x50]
  3d:	05 
  3e:	62 92 fd 49 5a 74 2e 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+r13*1+0x60]
  45:	06 
  46:	62 92 fd 49 5a 7c 2e 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+r13*1+0x70]
  4d:	07 
  4e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  55:	0f 1f 84 00 00 00 00 
  5c:	00 
  5d:	62 12 fd 49 5a 44 2e 	vbroadcasti64x2 zmm8{k1},XMMWORD PTR [r14+r13*1+0x80]
  64:	08 
  65:	62 12 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm9{k1},XMMWORD PTR [r14+r13*1+0x90]
  6c:	09 
  6d:	62 12 fd 49 5a 54 2e 	vbroadcasti64x2 zmm10{k1},XMMWORD PTR [r14+r13*1+0xa0]
  74:	0a 
  75:	62 12 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm11{k1},XMMWORD PTR [r14+r13*1+0xb0]
  7c:	0b 
  7d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  84:	0f 1f 84 00 00 00 00 
  8b:	00 
  8c:	62 12 fd 49 5a 64 2e 	vbroadcasti64x2 zmm12{k1},XMMWORD PTR [r14+r13*1+0xc0]
  93:	0c 
  94:	62 82 fd 49 5a 44 2e 	vbroadcasti64x2 zmm16{k1},XMMWORD PTR [r14+r13*1+0xd0]
  9b:	0d 
  9c:	62 82 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm17{k1},XMMWORD PTR [r14+r13*1+0xe0]
  a3:	0e 
  a4:	62 82 fd 49 5a 54 2e 	vbroadcasti64x2 zmm18{k1},XMMWORD PTR [r14+r13*1+0xf0]
  ab:	0f 
  ac:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  b3:	0f 1f 84 00 00 00 00 
  ba:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 22.0
- Core cycles: 8.02
- Reference cycles: 8.3
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 21.0
- UOPS_MITE: 6.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	62 92 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+r13*1+0x10]
   e:	01 
   f:	62 92 fd 49 5a 54 2e 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+r13*1+0x20]
  16:	02 
  17:	62 92 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+r13*1+0x30]
  1e:	03 
  1f:	62 92 fd 49 5a 64 2e 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+r13*1+0x40]
  26:	04 
  27:	62 92 fd 49 5a 6c 2e 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+r13*1+0x50]
  2e:	05 
  2f:	62 92 fd 49 5a 74 2e 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+r13*1+0x60]
  36:	06 
  37:	62 92 fd 49 5a 7c 2e 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+r13*1+0x70]
  3e:	07 
  3f:	62 12 fd 49 5a 44 2e 	vbroadcasti64x2 zmm8{k1},XMMWORD PTR [r14+r13*1+0x80]
  46:	08 
  47:	62 12 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm9{k1},XMMWORD PTR [r14+r13*1+0x90]
  4e:	09 
  4f:	62 12 fd 49 5a 54 2e 	vbroadcasti64x2 zmm10{k1},XMMWORD PTR [r14+r13*1+0xa0]
  56:	0a 
  57:	62 12 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm11{k1},XMMWORD PTR [r14+r13*1+0xb0]
  5e:	0b 
  5f:	62 12 fd 49 5a 64 2e 	vbroadcasti64x2 zmm12{k1},XMMWORD PTR [r14+r13*1+0xc0]
  66:	0c 
  67:	62 82 fd 49 5a 44 2e 	vbroadcasti64x2 zmm16{k1},XMMWORD PTR [r14+r13*1+0xd0]
  6e:	0d 
  6f:	62 82 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm17{k1},XMMWORD PTR [r14+r13*1+0xe0]
  76:	0e 
  77:	62 82 fd 49 5a 54 2e 	vbroadcasti64x2 zmm18{k1},XMMWORD PTR [r14+r13*1+0xf0]
  7e:	0f

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.02
- Reference cycles: 8.3
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 92 fd 49 5a 04 2e 	vbroadcasti64x2 zmm0{k1},XMMWORD PTR [r14+r13*1]
   7:	62 92 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm1{k1},XMMWORD PTR [r14+r13*1+0x10]
   e:	01 
   f:	62 92 fd 49 5a 54 2e 	vbroadcasti64x2 zmm2{k1},XMMWORD PTR [r14+r13*1+0x20]
  16:	02 
  17:	62 92 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm3{k1},XMMWORD PTR [r14+r13*1+0x30]
  1e:	03 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00 
  2e:	62 92 fd 49 5a 64 2e 	vbroadcasti64x2 zmm4{k1},XMMWORD PTR [r14+r13*1+0x40]
  35:	04 
  36:	62 92 fd 49 5a 6c 2e 	vbroadcasti64x2 zmm5{k1},XMMWORD PTR [r14+r13*1+0x50]
  3d:	05 
  3e:	62 92 fd 49 5a 74 2e 	vbroadcasti64x2 zmm6{k1},XMMWORD PTR [r14+r13*1+0x60]
  45:	06 
  46:	62 92 fd 49 5a 7c 2e 	vbroadcasti64x2 zmm7{k1},XMMWORD PTR [r14+r13*1+0x70]
  4d:	07 
  4e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  55:	0f 1f 84 00 00 00 00 
  5c:	00 
  5d:	62 12 fd 49 5a 44 2e 	vbroadcasti64x2 zmm8{k1},XMMWORD PTR [r14+r13*1+0x80]
  64:	08 
  65:	62 12 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm9{k1},XMMWORD PTR [r14+r13*1+0x90]
  6c:	09 
  6d:	62 12 fd 49 5a 54 2e 	vbroadcasti64x2 zmm10{k1},XMMWORD PTR [r14+r13*1+0xa0]
  74:	0a 
  75:	62 12 fd 49 5a 5c 2e 	vbroadcasti64x2 zmm11{k1},XMMWORD PTR [r14+r13*1+0xb0]
  7c:	0b 
  7d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  84:	0f 1f 84 00 00 00 00 
  8b:	00 
  8c:	62 12 fd 49 5a 64 2e 	vbroadcasti64x2 zmm12{k1},XMMWORD PTR [r14+r13*1+0xc0]
  93:	0c 
  94:	62 82 fd 49 5a 44 2e 	vbroadcasti64x2 zmm16{k1},XMMWORD PTR [r14+r13*1+0xd0]
  9b:	0d 
  9c:	62 82 fd 49 5a 4c 2e 	vbroadcasti64x2 zmm17{k1},XMMWORD PTR [r14+r13*1+0xe0]
  a3:	0e 
  a4:	62 82 fd 49 5a 54 2e 	vbroadcasti64x2 zmm18{k1},XMMWORD PTR [r14+r13*1+0xf0]
  ab:	0f 
  ac:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  b3:	0f 1f 84 00 00 00 00 
  ba:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM3, ZMM3, ZMM3;
VXORPS ZMM4, ZMM4, ZMM4;
VXORPS ZMM5, ZMM5, ZMM5;
VXORPS ZMM6, ZMM6, ZMM6;
VXORPS ZMM7, ZMM7, ZMM7;
VXORPS ZMM8, ZMM8, ZMM8;
VXORPS ZMM9, ZMM9, ZMM9;
VXORPS ZMM10, ZMM10, ZMM10;
VXORPS ZMM11, ZMM11, ZMM11;
VXORPS ZMM12, ZMM12, ZMM12;
VXORPS ZMM16, ZMM16, ZMM16;
VXORPS ZMM17, ZMM17, ZMM17;
VXORPS ZMM18, ZMM18, ZMM18

Show nanoBench command
Results:
- Instructions retired: 20.2
- Core cycles: 8.02
- Reference cycles: 8.3
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 20.1
- UOPS_MITE: 0.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.0
- UOPS_PORT_6: 0.11
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.09

VBROADCASTI64X2 (ZMM, K, M128) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (long NOPs)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (long NOPs)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (long NOPs)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (long NOPs)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (long NOPs)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (long NOPs)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (long NOPs)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (long NOPs)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)