VMOVDQU8 (M512, K, ZMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 2.0
- Reference cycles: 1.8
- UOPS_EXECUTED.THREAD: 5.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.81
- UOPS_PORT_3: 0.56
- UOPS_PORT_4: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.63
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.95
- UOPS_EXECUTED.THREAD: 5.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.67
- UOPS_PORT_3: 0.83
- UOPS_PORT_4: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	90                   	nop
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 2.0
- Reference cycles: 1.85
- UOPS_EXECUTED.THREAD: 5.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.8
- UOPS_PORT_3: 0.6
- UOPS_PORT_4: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.6
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 2.0
- Reference cycles: 1.9
- UOPS_EXECUTED.THREAD: 5.1
- RETIRE_SLOTS: 4.1
- UOPS_MITE: 4.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.78
- UOPS_PORT_3: 0.7
- UOPS_PORT_4: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.52
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   d:	0f 1f 84 00 00 00 00 
  14:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 2.0
- Reference cycles: 1.9
- UOPS_EXECUTED.THREAD: 5.1
- RETIRE_SLOTS: 5.1
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.7
- UOPS_PORT_3: 0.8
- UOPS_PORT_4: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 2.0
- Reference cycles: 1.9
- UOPS_EXECUTED.THREAD: 5.01
- RETIRE_SLOTS: 4.01
- UOPS_MITE: 4.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.84
- UOPS_PORT_3: 0.69
- UOPS_PORT_4: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.46
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (long NOPs)

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   d:	0f 1f 84 00 00 00 00 
  14:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 2.0
- Reference cycles: 2.01
- UOPS_EXECUTED.THREAD: 5.01
- RETIRE_SLOTS: 5.01
- UOPS_MITE: 0.05
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.67
- UOPS_PORT_3: 0.84
- UOPS_PORT_4: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d1 7f 49 7f 46 01 	vmovdqu8 ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d1 7f 49 7f 46 02 	vmovdqu8 ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d1 7f 49 7f 46 03 	vmovdqu8 ZMMWORD PTR [r14+0xc0]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 8.0
- Reference cycles: 8.03
- UOPS_EXECUTED.THREAD: 20.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 3.25
- UOPS_PORT_3: 2.25
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 2.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d1 7f 49 7f 46 01 	vmovdqu8 ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d1 7f 49 7f 46 02 	vmovdqu8 ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d1 7f 49 7f 46 03 	vmovdqu8 ZMMWORD PTR [r14+0xc0]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 8.01
- Reference cycles: 7.57
- UOPS_EXECUTED.THREAD: 20.5
- RETIRE_SLOTS: 16.5
- UOPS_MITE: 16.53
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 3.16
- UOPS_PORT_3: 3.0
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 1.84
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.01

With loop_count=1000, unroll_count=2, and padding (long NOPs)

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d1 7f 49 7f 46 01 	vmovdqu8 ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d1 7f 49 7f 46 02 	vmovdqu8 ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d1 7f 49 7f 46 03 	vmovdqu8 ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  22:	0f 1f 84 00 00 00 00 
  29:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.01
- Reference cycles: 7.59
- UOPS_EXECUTED.THREAD: 20.5
- RETIRE_SLOTS: 17.5
- UOPS_MITE: 17.53
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 3.0
- UOPS_PORT_3: 3.19
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 1.82
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.51

With loop_count=100 and unroll_count=20

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d1 7f 49 7f 46 01 	vmovdqu8 ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d1 7f 49 7f 46 02 	vmovdqu8 ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d1 7f 49 7f 46 03 	vmovdqu8 ZMMWORD PTR [r14+0xc0]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 8.01
- Reference cycles: 7.59
- UOPS_EXECUTED.THREAD: 20.05
- RETIRE_SLOTS: 16.05
- UOPS_MITE: 16.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 3.25
- UOPS_PORT_3: 2.88
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 1.87
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.01

With loop_count=100, unroll_count=20, and padding (long NOPs)

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d1 7f 49 7f 46 01 	vmovdqu8 ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d1 7f 49 7f 46 02 	vmovdqu8 ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d1 7f 49 7f 46 03 	vmovdqu8 ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  22:	0f 1f 84 00 00 00 00 
  29:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 5.1
- Core cycles: 8.01
- Reference cycles: 7.59
- UOPS_EXECUTED.THREAD: 20.05
- RETIRE_SLOTS: 17.05
- UOPS_MITE: 17.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 2.85
- UOPS_PORT_3: 3.24
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 1.91
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.06

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d1 7f 49 7f 46 01 	vmovdqu8 ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d1 7f 49 7f 46 02 	vmovdqu8 ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d1 7f 49 7f 46 03 	vmovdqu8 ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	62 d1 7f 49 7f 46 04 	vmovdqu8 ZMMWORD PTR [r14+0x100]{k1},zmm0
  22:	62 d1 7f 49 7f 46 05 	vmovdqu8 ZMMWORD PTR [r14+0x140]{k1},zmm0
  29:	62 d1 7f 49 7f 46 06 	vmovdqu8 ZMMWORD PTR [r14+0x180]{k1},zmm0
  30:	62 d1 7f 49 7f 46 07 	vmovdqu8 ZMMWORD PTR [r14+0x1c0]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 16.0
- Reference cycles: 15.57
- UOPS_EXECUTED.THREAD: 40.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 6.5
- UOPS_PORT_3: 4.5
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 5.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d1 7f 49 7f 46 01 	vmovdqu8 ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d1 7f 49 7f 46 02 	vmovdqu8 ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d1 7f 49 7f 46 03 	vmovdqu8 ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	62 d1 7f 49 7f 46 04 	vmovdqu8 ZMMWORD PTR [r14+0x100]{k1},zmm0
  22:	62 d1 7f 49 7f 46 05 	vmovdqu8 ZMMWORD PTR [r14+0x140]{k1},zmm0
  29:	62 d1 7f 49 7f 46 06 	vmovdqu8 ZMMWORD PTR [r14+0x180]{k1},zmm0
  30:	62 d1 7f 49 7f 46 07 	vmovdqu8 ZMMWORD PTR [r14+0x1c0]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 16.01
- Reference cycles: 15.18
- UOPS_EXECUTED.THREAD: 41.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 33.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 6.31
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 3.69
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d1 7f 49 7f 46 01 	vmovdqu8 ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d1 7f 49 7f 46 02 	vmovdqu8 ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d1 7f 49 7f 46 03 	vmovdqu8 ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  22:	0f 1f 84 00 00 00 00 
  29:	00 
  2a:	62 d1 7f 49 7f 46 04 	vmovdqu8 ZMMWORD PTR [r14+0x100]{k1},zmm0
  31:	62 d1 7f 49 7f 46 05 	vmovdqu8 ZMMWORD PTR [r14+0x140]{k1},zmm0
  38:	62 d1 7f 49 7f 46 06 	vmovdqu8 ZMMWORD PTR [r14+0x180]{k1},zmm0
  3f:	62 d1 7f 49 7f 46 07 	vmovdqu8 ZMMWORD PTR [r14+0x1c0]{k1},zmm0
  46:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  4d:	0f 1f 84 00 00 00 00 
  54:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 16.01
- Reference cycles: 15.18
- UOPS_EXECUTED.THREAD: 41.01
- RETIRE_SLOTS: 35.0
- UOPS_MITE: 35.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 6.0
- UOPS_PORT_3: 6.37
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 3.63
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 9.02

With loop_count=100 and unroll_count=10

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d1 7f 49 7f 46 01 	vmovdqu8 ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d1 7f 49 7f 46 02 	vmovdqu8 ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d1 7f 49 7f 46 03 	vmovdqu8 ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	62 d1 7f 49 7f 46 04 	vmovdqu8 ZMMWORD PTR [r14+0x100]{k1},zmm0
  22:	62 d1 7f 49 7f 46 05 	vmovdqu8 ZMMWORD PTR [r14+0x140]{k1},zmm0
  29:	62 d1 7f 49 7f 46 06 	vmovdqu8 ZMMWORD PTR [r14+0x180]{k1},zmm0
  30:	62 d1 7f 49 7f 46 07 	vmovdqu8 ZMMWORD PTR [r14+0x1c0]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 16.01
- Reference cycles: 15.11
- UOPS_EXECUTED.THREAD: 40.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 32.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 6.5
- UOPS_PORT_3: 5.75
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 3.75
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.01

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d1 7f 49 7f 46 01 	vmovdqu8 ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d1 7f 49 7f 46 02 	vmovdqu8 ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d1 7f 49 7f 46 03 	vmovdqu8 ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  22:	0f 1f 84 00 00 00 00 
  29:	00 
  2a:	62 d1 7f 49 7f 46 04 	vmovdqu8 ZMMWORD PTR [r14+0x100]{k1},zmm0
  31:	62 d1 7f 49 7f 46 05 	vmovdqu8 ZMMWORD PTR [r14+0x140]{k1},zmm0
  38:	62 d1 7f 49 7f 46 06 	vmovdqu8 ZMMWORD PTR [r14+0x180]{k1},zmm0
  3f:	62 d1 7f 49 7f 46 07 	vmovdqu8 ZMMWORD PTR [r14+0x1c0]{k1},zmm0
  46:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  4d:	0f 1f 84 00 00 00 00 
  54:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 10.2
- Core cycles: 16.01
- Reference cycles: 15.18
- UOPS_EXECUTED.THREAD: 40.11
- RETIRE_SLOTS: 34.1
- UOPS_MITE: 34.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 5.7
- UOPS_PORT_3: 6.49
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 3.82
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.12

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d1 7f 49 7f 46 01 	vmovdqu8 ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d1 7f 49 7f 46 02 	vmovdqu8 ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d1 7f 49 7f 46 03 	vmovdqu8 ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	62 d1 7f 49 7f 46 04 	vmovdqu8 ZMMWORD PTR [r14+0x100]{k1},zmm0
  22:	62 d1 7f 49 7f 46 05 	vmovdqu8 ZMMWORD PTR [r14+0x140]{k1},zmm0
  29:	62 d1 7f 49 7f 46 06 	vmovdqu8 ZMMWORD PTR [r14+0x180]{k1},zmm0
  30:	62 d1 7f 49 7f 46 07 	vmovdqu8 ZMMWORD PTR [r14+0x1c0]{k1},zmm0
  37:	62 d1 7f 49 7f 46 08 	vmovdqu8 ZMMWORD PTR [r14+0x200]{k1},zmm0
  3e:	62 d1 7f 49 7f 46 09 	vmovdqu8 ZMMWORD PTR [r14+0x240]{k1},zmm0
  45:	62 d1 7f 49 7f 46 0a 	vmovdqu8 ZMMWORD PTR [r14+0x280]{k1},zmm0
  4c:	62 d1 7f 49 7f 46 0b 	vmovdqu8 ZMMWORD PTR [r14+0x2c0]{k1},zmm0
  53:	62 d1 7f 49 7f 46 0c 	vmovdqu8 ZMMWORD PTR [r14+0x300]{k1},zmm0
  5a:	62 d1 7f 49 7f 46 0d 	vmovdqu8 ZMMWORD PTR [r14+0x340]{k1},zmm0
  61:	62 d1 7f 49 7f 46 0e 	vmovdqu8 ZMMWORD PTR [r14+0x380]{k1},zmm0
  68:	62 d1 7f 49 7f 46 0f 	vmovdqu8 ZMMWORD PTR [r14+0x3c0]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 32.09
- Reference cycles: 30.17
- UOPS_EXECUTED.THREAD: 80.0
- RETIRE_SLOTS: 64.0
- UOPS_MITE: 64.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 16.0
- UOPS_PORT_2: 12.98
- UOPS_PORT_3: 9.01
- UOPS_PORT_4: 32.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 10.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d1 7f 49 7f 46 01 	vmovdqu8 ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d1 7f 49 7f 46 02 	vmovdqu8 ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d1 7f 49 7f 46 03 	vmovdqu8 ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	62 d1 7f 49 7f 46 04 	vmovdqu8 ZMMWORD PTR [r14+0x100]{k1},zmm0
  22:	62 d1 7f 49 7f 46 05 	vmovdqu8 ZMMWORD PTR [r14+0x140]{k1},zmm0
  29:	62 d1 7f 49 7f 46 06 	vmovdqu8 ZMMWORD PTR [r14+0x180]{k1},zmm0
  30:	62 d1 7f 49 7f 46 07 	vmovdqu8 ZMMWORD PTR [r14+0x1c0]{k1},zmm0
  37:	62 d1 7f 49 7f 46 08 	vmovdqu8 ZMMWORD PTR [r14+0x200]{k1},zmm0
  3e:	62 d1 7f 49 7f 46 09 	vmovdqu8 ZMMWORD PTR [r14+0x240]{k1},zmm0
  45:	62 d1 7f 49 7f 46 0a 	vmovdqu8 ZMMWORD PTR [r14+0x280]{k1},zmm0
  4c:	62 d1 7f 49 7f 46 0b 	vmovdqu8 ZMMWORD PTR [r14+0x2c0]{k1},zmm0
  53:	62 d1 7f 49 7f 46 0c 	vmovdqu8 ZMMWORD PTR [r14+0x300]{k1},zmm0
  5a:	62 d1 7f 49 7f 46 0d 	vmovdqu8 ZMMWORD PTR [r14+0x340]{k1},zmm0
  61:	62 d1 7f 49 7f 46 0e 	vmovdqu8 ZMMWORD PTR [r14+0x380]{k1},zmm0
  68:	62 d1 7f 49 7f 46 0f 	vmovdqu8 ZMMWORD PTR [r14+0x3c0]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 32.01
- Reference cycles: 30.37
- UOPS_EXECUTED.THREAD: 81.01
- RETIRE_SLOTS: 65.0
- UOPS_MITE: 65.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 16.0
- UOPS_PORT_2: 12.81
- UOPS_PORT_3: 11.66
- UOPS_PORT_4: 32.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 7.53
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d1 7f 49 7f 46 01 	vmovdqu8 ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d1 7f 49 7f 46 02 	vmovdqu8 ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d1 7f 49 7f 46 03 	vmovdqu8 ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  22:	0f 1f 84 00 00 00 00 
  29:	00 
  2a:	62 d1 7f 49 7f 46 04 	vmovdqu8 ZMMWORD PTR [r14+0x100]{k1},zmm0
  31:	62 d1 7f 49 7f 46 05 	vmovdqu8 ZMMWORD PTR [r14+0x140]{k1},zmm0
  38:	62 d1 7f 49 7f 46 06 	vmovdqu8 ZMMWORD PTR [r14+0x180]{k1},zmm0
  3f:	62 d1 7f 49 7f 46 07 	vmovdqu8 ZMMWORD PTR [r14+0x1c0]{k1},zmm0
  46:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  4d:	0f 1f 84 00 00 00 00 
  54:	00 
  55:	62 d1 7f 49 7f 46 08 	vmovdqu8 ZMMWORD PTR [r14+0x200]{k1},zmm0
  5c:	62 d1 7f 49 7f 46 09 	vmovdqu8 ZMMWORD PTR [r14+0x240]{k1},zmm0
  63:	62 d1 7f 49 7f 46 0a 	vmovdqu8 ZMMWORD PTR [r14+0x280]{k1},zmm0
  6a:	62 d1 7f 49 7f 46 0b 	vmovdqu8 ZMMWORD PTR [r14+0x2c0]{k1},zmm0
  71:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  78:	0f 1f 84 00 00 00 00 
  7f:	00 
  80:	62 d1 7f 49 7f 46 0c 	vmovdqu8 ZMMWORD PTR [r14+0x300]{k1},zmm0
  87:	62 d1 7f 49 7f 46 0d 	vmovdqu8 ZMMWORD PTR [r14+0x340]{k1},zmm0
  8e:	62 d1 7f 49 7f 46 0e 	vmovdqu8 ZMMWORD PTR [r14+0x380]{k1},zmm0
  95:	62 d1 7f 49 7f 46 0f 	vmovdqu8 ZMMWORD PTR [r14+0x3c0]{k1},zmm0
  9c:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  a3:	0f 1f 84 00 00 00 00 
  aa:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 22.0
- Core cycles: 32.01
- Reference cycles: 30.34
- UOPS_EXECUTED.THREAD: 81.01
- RETIRE_SLOTS: 69.0
- UOPS_MITE: 69.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 16.0
- UOPS_PORT_2: 11.5
- UOPS_PORT_3: 12.51
- UOPS_PORT_4: 32.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 7.78
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 17.02

With loop_count=100 and unroll_count=10

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d1 7f 49 7f 46 01 	vmovdqu8 ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d1 7f 49 7f 46 02 	vmovdqu8 ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d1 7f 49 7f 46 03 	vmovdqu8 ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	62 d1 7f 49 7f 46 04 	vmovdqu8 ZMMWORD PTR [r14+0x100]{k1},zmm0
  22:	62 d1 7f 49 7f 46 05 	vmovdqu8 ZMMWORD PTR [r14+0x140]{k1},zmm0
  29:	62 d1 7f 49 7f 46 06 	vmovdqu8 ZMMWORD PTR [r14+0x180]{k1},zmm0
  30:	62 d1 7f 49 7f 46 07 	vmovdqu8 ZMMWORD PTR [r14+0x1c0]{k1},zmm0
  37:	62 d1 7f 49 7f 46 08 	vmovdqu8 ZMMWORD PTR [r14+0x200]{k1},zmm0
  3e:	62 d1 7f 49 7f 46 09 	vmovdqu8 ZMMWORD PTR [r14+0x240]{k1},zmm0
  45:	62 d1 7f 49 7f 46 0a 	vmovdqu8 ZMMWORD PTR [r14+0x280]{k1},zmm0
  4c:	62 d1 7f 49 7f 46 0b 	vmovdqu8 ZMMWORD PTR [r14+0x2c0]{k1},zmm0
  53:	62 d1 7f 49 7f 46 0c 	vmovdqu8 ZMMWORD PTR [r14+0x300]{k1},zmm0
  5a:	62 d1 7f 49 7f 46 0d 	vmovdqu8 ZMMWORD PTR [r14+0x340]{k1},zmm0
  61:	62 d1 7f 49 7f 46 0e 	vmovdqu8 ZMMWORD PTR [r14+0x380]{k1},zmm0
  68:	62 d1 7f 49 7f 46 0f 	vmovdqu8 ZMMWORD PTR [r14+0x3c0]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 32.01
- Reference cycles: 30.37
- UOPS_EXECUTED.THREAD: 80.11
- RETIRE_SLOTS: 64.1
- UOPS_MITE: 64.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 16.0
- UOPS_PORT_2: 13.08
- UOPS_PORT_3: 11.48
- UOPS_PORT_4: 32.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.11
- UOPS_PORT_7: 7.45
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.02

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 d1 7f 49 7f 06    	vmovdqu8 ZMMWORD PTR [r14]{k1},zmm0
   6:	62 d1 7f 49 7f 46 01 	vmovdqu8 ZMMWORD PTR [r14+0x40]{k1},zmm0
   d:	62 d1 7f 49 7f 46 02 	vmovdqu8 ZMMWORD PTR [r14+0x80]{k1},zmm0
  14:	62 d1 7f 49 7f 46 03 	vmovdqu8 ZMMWORD PTR [r14+0xc0]{k1},zmm0
  1b:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  22:	0f 1f 84 00 00 00 00 
  29:	00 
  2a:	62 d1 7f 49 7f 46 04 	vmovdqu8 ZMMWORD PTR [r14+0x100]{k1},zmm0
  31:	62 d1 7f 49 7f 46 05 	vmovdqu8 ZMMWORD PTR [r14+0x140]{k1},zmm0
  38:	62 d1 7f 49 7f 46 06 	vmovdqu8 ZMMWORD PTR [r14+0x180]{k1},zmm0
  3f:	62 d1 7f 49 7f 46 07 	vmovdqu8 ZMMWORD PTR [r14+0x1c0]{k1},zmm0
  46:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  4d:	0f 1f 84 00 00 00 00 
  54:	00 
  55:	62 d1 7f 49 7f 46 08 	vmovdqu8 ZMMWORD PTR [r14+0x200]{k1},zmm0
  5c:	62 d1 7f 49 7f 46 09 	vmovdqu8 ZMMWORD PTR [r14+0x240]{k1},zmm0
  63:	62 d1 7f 49 7f 46 0a 	vmovdqu8 ZMMWORD PTR [r14+0x280]{k1},zmm0
  6a:	62 d1 7f 49 7f 46 0b 	vmovdqu8 ZMMWORD PTR [r14+0x2c0]{k1},zmm0
  71:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  78:	0f 1f 84 00 00 00 00 
  7f:	00 
  80:	62 d1 7f 49 7f 46 0c 	vmovdqu8 ZMMWORD PTR [r14+0x300]{k1},zmm0
  87:	62 d1 7f 49 7f 46 0d 	vmovdqu8 ZMMWORD PTR [r14+0x340]{k1},zmm0
  8e:	62 d1 7f 49 7f 46 0e 	vmovdqu8 ZMMWORD PTR [r14+0x380]{k1},zmm0
  95:	62 d1 7f 49 7f 46 0f 	vmovdqu8 ZMMWORD PTR [r14+0x3c0]{k1},zmm0
  9c:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  a3:	0f 1f 84 00 00 00 00 
  aa:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 20.2
- Core cycles: 32.01
- Reference cycles: 30.37
- UOPS_EXECUTED.THREAD: 80.11
- RETIRE_SLOTS: 68.1
- UOPS_MITE: 68.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 16.0
- UOPS_PORT_2: 11.37
- UOPS_PORT_3: 12.83
- UOPS_PORT_4: 32.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 7.81
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.12

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 2.0
- Reference cycles: 2.09
- UOPS_EXECUTED.THREAD: 5.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 1.0
- UOPS_PORT_4: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.85
- UOPS_EXECUTED.THREAD: 5.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 1.0
- UOPS_PORT_4: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	90                   	nop
   8:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 2.0
- Reference cycles: 2.14
- UOPS_EXECUTED.THREAD: 5.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 1.0
- UOPS_PORT_4: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 2.0
- Reference cycles: 2.07
- UOPS_EXECUTED.THREAD: 5.1
- RETIRE_SLOTS: 4.1
- UOPS_MITE: 4.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 1.0
- UOPS_PORT_4: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   e:	0f 1f 84 00 00 00 00 
  15:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 2.0
- Reference cycles: 2.06
- UOPS_EXECUTED.THREAD: 5.1
- RETIRE_SLOTS: 5.1
- UOPS_MITE: 0.61
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 0.98
- UOPS_PORT_3: 1.02
- UOPS_PORT_4: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.2

With loop_count=100 and unroll_count=100

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 2.0
- Reference cycles: 2.01
- UOPS_EXECUTED.THREAD: 5.01
- RETIRE_SLOTS: 4.01
- UOPS_MITE: 4.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 1.0
- UOPS_PORT_4: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (long NOPs)

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
   e:	0f 1f 84 00 00 00 00 
  15:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 2.0
- Reference cycles: 2.07
- UOPS_EXECUTED.THREAD: 5.01
- RETIRE_SLOTS: 5.01
- UOPS_MITE: 0.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 1.0
- UOPS_PORT_4: 2.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	01 
   f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	02 
  17:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	03

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 8.0
- Reference cycles: 8.76
- UOPS_EXECUTED.THREAD: 20.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	01 
   f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	02 
  17:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	03

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 8.01
- Reference cycles: 8.27
- UOPS_EXECUTED.THREAD: 20.5
- RETIRE_SLOTS: 16.5
- UOPS_MITE: 16.53
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 3.96
- UOPS_PORT_3: 4.04
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.01

With loop_count=1000, unroll_count=2, and padding (long NOPs)

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	01 
   f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	02 
  17:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	03 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.01
- Reference cycles: 7.59
- UOPS_EXECUTED.THREAD: 20.5
- RETIRE_SLOTS: 17.5
- UOPS_MITE: 17.53
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 3.85
- UOPS_PORT_3: 4.16
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.51

With loop_count=100 and unroll_count=20

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	01 
   f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	02 
  17:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	03

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 8.01
- Reference cycles: 7.59
- UOPS_EXECUTED.THREAD: 20.05
- RETIRE_SLOTS: 16.05
- UOPS_MITE: 16.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.01
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.01

With loop_count=100, unroll_count=20, and padding (long NOPs)

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	01 
   f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	02 
  17:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	03 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 5.1
- Core cycles: 8.01
- Reference cycles: 7.59
- UOPS_EXECUTED.THREAD: 20.05
- RETIRE_SLOTS: 17.05
- UOPS_MITE: 17.08
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 3.99
- UOPS_PORT_3: 4.02
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.06

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	01 
   f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	02 
  17:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	03 
  1f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  26:	04 
  27:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  2e:	05 
  2f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  36:	06 
  37:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  3e:	07

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 16.0
- Reference cycles: 17.52
- UOPS_EXECUTED.THREAD: 40.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	01 
   f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	02 
  17:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	03 
  1f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  26:	04 
  27:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  2e:	05 
  2f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  36:	06 
  37:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  3e:	07

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 16.02
- Reference cycles: 16.5
- UOPS_EXECUTED.THREAD: 41.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 33.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 7.92
- UOPS_PORT_3: 8.08
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	01 
   f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	02 
  17:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	03 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00 
  2e:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  35:	04 
  36:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  3d:	05 
  3e:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  45:	06 
  46:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  4d:	07 
  4e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  55:	0f 1f 84 00 00 00 00 
  5c:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 16.01
- Reference cycles: 15.16
- UOPS_EXECUTED.THREAD: 41.01
- RETIRE_SLOTS: 35.0
- UOPS_MITE: 35.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 7.69
- UOPS_PORT_3: 8.31
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 9.02

With loop_count=100 and unroll_count=10

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	01 
   f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	02 
  17:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	03 
  1f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  26:	04 
  27:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  2e:	05 
  2f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  36:	06 
  37:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  3e:	07

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 16.01
- Reference cycles: 15.18
- UOPS_EXECUTED.THREAD: 40.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 32.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 7.99
- UOPS_PORT_2: 7.99
- UOPS_PORT_3: 8.02
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.11
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.02

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	01 
   f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	02 
  17:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	03 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00 
  2e:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  35:	04 
  36:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  3d:	05 
  3e:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  45:	06 
  46:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  4d:	07 
  4e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  55:	0f 1f 84 00 00 00 00 
  5c:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.2
- Core cycles: 16.01
- Reference cycles: 15.18
- UOPS_EXECUTED.THREAD: 40.11
- RETIRE_SLOTS: 34.1
- UOPS_MITE: 34.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_2: 7.97
- UOPS_PORT_3: 8.03
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.11

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	01 
   f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	02 
  17:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	03 
  1f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  26:	04 
  27:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  2e:	05 
  2f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  36:	06 
  37:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  3e:	07 
  3f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x200]{k1},zmm0
  46:	08 
  47:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x240]{k1},zmm0
  4e:	09 
  4f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x280]{k1},zmm0
  56:	0a 
  57:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x2c0]{k1},zmm0
  5e:	0b 
  5f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x300]{k1},zmm0
  66:	0c 
  67:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x340]{k1},zmm0
  6e:	0d 
  6f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x380]{k1},zmm0
  76:	0e 
  77:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x3c0]{k1},zmm0
  7e:	0f

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 32.09
- Reference cycles: 30.66
- UOPS_EXECUTED.THREAD: 80.0
- RETIRE_SLOTS: 64.0
- UOPS_MITE: 64.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 16.0
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 16.0
- UOPS_PORT_4: 32.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	01 
   f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	02 
  17:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	03 
  1f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  26:	04 
  27:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  2e:	05 
  2f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  36:	06 
  37:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  3e:	07 
  3f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x200]{k1},zmm0
  46:	08 
  47:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x240]{k1},zmm0
  4e:	09 
  4f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x280]{k1},zmm0
  56:	0a 
  57:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x2c0]{k1},zmm0
  5e:	0b 
  5f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x300]{k1},zmm0
  66:	0c 
  67:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x340]{k1},zmm0
  6e:	0d 
  6f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x380]{k1},zmm0
  76:	0e 
  77:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x3c0]{k1},zmm0
  7e:	0f

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 32.01
- Reference cycles: 30.3
- UOPS_EXECUTED.THREAD: 81.01
- RETIRE_SLOTS: 65.0
- UOPS_MITE: 65.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 16.0
- UOPS_PORT_2: 15.88
- UOPS_PORT_3: 16.13
- UOPS_PORT_4: 32.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.02

With loop_count=1000, unroll_count=1, and padding (long NOPs)

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	01 
   f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	02 
  17:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	03 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00 
  2e:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  35:	04 
  36:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  3d:	05 
  3e:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  45:	06 
  46:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  4d:	07 
  4e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  55:	0f 1f 84 00 00 00 00 
  5c:	00 
  5d:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x200]{k1},zmm0
  64:	08 
  65:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x240]{k1},zmm0
  6c:	09 
  6d:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x280]{k1},zmm0
  74:	0a 
  75:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x2c0]{k1},zmm0
  7c:	0b 
  7d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  84:	0f 1f 84 00 00 00 00 
  8b:	00 
  8c:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x300]{k1},zmm0
  93:	0c 
  94:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x340]{k1},zmm0
  9b:	0d 
  9c:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x380]{k1},zmm0
  a3:	0e 
  a4:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x3c0]{k1},zmm0
  ab:	0f 
  ac:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  b3:	0f 1f 84 00 00 00 00 
  ba:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 22.0
- Core cycles: 32.01
- Reference cycles: 30.37
- UOPS_EXECUTED.THREAD: 81.01
- RETIRE_SLOTS: 69.0
- UOPS_MITE: 69.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 16.0
- UOPS_PORT_2: 15.94
- UOPS_PORT_3: 16.07
- UOPS_PORT_4: 32.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 17.02

With loop_count=100 and unroll_count=10

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	01 
   f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	02 
  17:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	03 
  1f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  26:	04 
  27:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  2e:	05 
  2f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  36:	06 
  37:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  3e:	07 
  3f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x200]{k1},zmm0
  46:	08 
  47:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x240]{k1},zmm0
  4e:	09 
  4f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x280]{k1},zmm0
  56:	0a 
  57:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x2c0]{k1},zmm0
  5e:	0b 
  5f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x300]{k1},zmm0
  66:	0c 
  67:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x340]{k1},zmm0
  6e:	0d 
  6f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x380]{k1},zmm0
  76:	0e 
  77:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x3c0]{k1},zmm0
  7e:	0f

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 32.01
- Reference cycles: 30.32
- UOPS_EXECUTED.THREAD: 80.1
- RETIRE_SLOTS: 64.1
- UOPS_MITE: 64.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 15.99
- UOPS_PORT_2: 15.95
- UOPS_PORT_3: 16.05
- UOPS_PORT_4: 32.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.11
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.02

With loop_count=100, unroll_count=10, and padding (long NOPs)

Code:

   0:	62 91 7f 49 7f 04 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1]{k1},zmm0
   7:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x40]{k1},zmm0
   e:	01 
   f:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x80]{k1},zmm0
  16:	02 
  17:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0xc0]{k1},zmm0
  1e:	03 
  1f:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  26:	0f 1f 84 00 00 00 00 
  2d:	00 
  2e:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x100]{k1},zmm0
  35:	04 
  36:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x140]{k1},zmm0
  3d:	05 
  3e:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x180]{k1},zmm0
  45:	06 
  46:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x1c0]{k1},zmm0
  4d:	07 
  4e:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  55:	0f 1f 84 00 00 00 00 
  5c:	00 
  5d:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x200]{k1},zmm0
  64:	08 
  65:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x240]{k1},zmm0
  6c:	09 
  6d:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x280]{k1},zmm0
  74:	0a 
  75:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x2c0]{k1},zmm0
  7c:	0b 
  7d:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  84:	0f 1f 84 00 00 00 00 
  8b:	00 
  8c:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x300]{k1},zmm0
  93:	0c 
  94:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x340]{k1},zmm0
  9b:	0d 
  9c:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x380]{k1},zmm0
  a3:	0e 
  a4:	62 91 7f 49 7f 44 2e 	vmovdqu8 ZMMWORD PTR [r14+r13*1+0x3c0]{k1},zmm0
  ab:	0f 
  ac:	66 66 66 66 66 66 2e 	data16 data16 data16 data16 data16 cs nop WORD PTR [rax+rax*1+0x0]
  b3:	0f 1f 84 00 00 00 00 
  ba:	00

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 20.2
- Core cycles: 32.01
- Reference cycles: 30.37
- UOPS_EXECUTED.THREAD: 80.11
- RETIRE_SLOTS: 68.1
- UOPS_MITE: 68.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.0
- UOPS_PORT_1: 16.0
- UOPS_PORT_2: 15.91
- UOPS_PORT_3: 16.1
- UOPS_PORT_4: 32.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.12

VMOVDQU8 (M512, K, ZMM) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (long NOPs)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (long NOPs)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (long NOPs)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (long NOPs)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (long NOPs)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (long NOPs)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (long NOPs)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (long NOPs)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (long NOPs)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (long NOPs)