VPADDD (XMM, K, XMM, XMM)

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 75 09 fe c2    	vpaddd xmm0{k1},xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.88
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.34
- UOPS_PORT_1: 0.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.33
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 75 09 fe c2    	vpaddd xmm0{k1},xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.9
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 1.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.34
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.3

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 75 09 fe c2    	vpaddd xmm0{k1},xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.9
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.34
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f1 75 09 fe c2    	vpaddd xmm0{k1},xmm1,xmm2
   6:	62 f1 75 09 fe da    	vpaddd xmm3{k1},xmm1,xmm2
   c:	62 f1 75 09 fe e2    	vpaddd xmm4{k1},xmm1,xmm2
  12:	62 f1 75 09 fe ea    	vpaddd xmm5{k1},xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.5
- Reference cycles: 1.34
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.29
- UOPS_PORT_1: 1.34
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.38
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.5

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f1 75 09 fe c2    	vpaddd xmm0{k1},xmm1,xmm2
   6:	62 f1 75 09 fe da    	vpaddd xmm3{k1},xmm1,xmm2
   c:	62 f1 75 09 fe e2    	vpaddd xmm4{k1},xmm1,xmm2
  12:	62 f1 75 09 fe ea    	vpaddd xmm5{k1},xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.51
- Reference cycles: 1.35
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.31
- UOPS_PORT_1: 1.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.36
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f1 75 09 fe c2    	vpaddd xmm0{k1},xmm1,xmm2
   6:	62 f1 75 09 fe da    	vpaddd xmm3{k1},xmm1,xmm2
   c:	62 f1 75 09 fe e2    	vpaddd xmm4{k1},xmm1,xmm2
  12:	62 f1 75 09 fe ea    	vpaddd xmm5{k1},xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 1.36
- Reference cycles: 1.22
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.32
- UOPS_PORT_1: 1.34
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.34
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 75 09 fe c2    	vpaddd xmm0{k1},xmm1,xmm2
   6:	62 f1 75 09 fe da    	vpaddd xmm3{k1},xmm1,xmm2
   c:	62 f1 75 09 fe e2    	vpaddd xmm4{k1},xmm1,xmm2
  12:	62 f1 75 09 fe ea    	vpaddd xmm5{k1},xmm1,xmm2
  18:	62 f1 75 09 fe f2    	vpaddd xmm6{k1},xmm1,xmm2
  1e:	62 f1 75 09 fe fa    	vpaddd xmm7{k1},xmm1,xmm2
  24:	62 71 75 09 fe c2    	vpaddd xmm8{k1},xmm1,xmm2
  2a:	62 71 75 09 fe ca    	vpaddd xmm9{k1},xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 3.0
- Reference cycles: 2.92
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.63
- UOPS_PORT_1: 2.67
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.7
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 75 09 fe c2    	vpaddd xmm0{k1},xmm1,xmm2
   6:	62 f1 75 09 fe da    	vpaddd xmm3{k1},xmm1,xmm2
   c:	62 f1 75 09 fe e2    	vpaddd xmm4{k1},xmm1,xmm2
  12:	62 f1 75 09 fe ea    	vpaddd xmm5{k1},xmm1,xmm2
  18:	62 f1 75 09 fe f2    	vpaddd xmm6{k1},xmm1,xmm2
  1e:	62 f1 75 09 fe fa    	vpaddd xmm7{k1},xmm1,xmm2
  24:	62 71 75 09 fe c2    	vpaddd xmm8{k1},xmm1,xmm2
  2a:	62 71 75 09 fe ca    	vpaddd xmm9{k1},xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 2.68
- Reference cycles: 2.43
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.67
- UOPS_PORT_1: 2.67
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.67
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 75 09 fe c2    	vpaddd xmm0{k1},xmm1,xmm2
   6:	62 f1 75 09 fe da    	vpaddd xmm3{k1},xmm1,xmm2
   c:	62 f1 75 09 fe e2    	vpaddd xmm4{k1},xmm1,xmm2
  12:	62 f1 75 09 fe ea    	vpaddd xmm5{k1},xmm1,xmm2
  18:	62 f1 75 09 fe f2    	vpaddd xmm6{k1},xmm1,xmm2
  1e:	62 f1 75 09 fe fa    	vpaddd xmm7{k1},xmm1,xmm2
  24:	62 71 75 09 fe c2    	vpaddd xmm8{k1},xmm1,xmm2
  2a:	62 71 75 09 fe ca    	vpaddd xmm9{k1},xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 2.68
- Reference cycles: 2.36
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.09
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.67
- UOPS_PORT_1: 2.67
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.67
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 75 09 fe c2    	vpaddd xmm0{k1},xmm1,xmm2
   6:	62 f1 75 09 fe da    	vpaddd xmm3{k1},xmm1,xmm2
   c:	62 f1 75 09 fe e2    	vpaddd xmm4{k1},xmm1,xmm2
  12:	62 f1 75 09 fe ea    	vpaddd xmm5{k1},xmm1,xmm2
  18:	62 f1 75 09 fe f2    	vpaddd xmm6{k1},xmm1,xmm2
  1e:	62 f1 75 09 fe fa    	vpaddd xmm7{k1},xmm1,xmm2
  24:	62 71 75 09 fe c2    	vpaddd xmm8{k1},xmm1,xmm2
  2a:	62 71 75 09 fe ca    	vpaddd xmm9{k1},xmm1,xmm2
  30:	62 71 75 09 fe d2    	vpaddd xmm10{k1},xmm1,xmm2
  36:	62 71 75 09 fe da    	vpaddd xmm11{k1},xmm1,xmm2
  3c:	62 71 75 09 fe e2    	vpaddd xmm12{k1},xmm1,xmm2
  42:	62 e1 75 09 fe c2    	vpaddd xmm16{k1},xmm1,xmm2
  48:	62 e1 75 09 fe ca    	vpaddd xmm17{k1},xmm1,xmm2
  4e:	62 e1 75 09 fe d2    	vpaddd xmm18{k1},xmm1,xmm2
  54:	62 e1 75 09 fe da    	vpaddd xmm19{k1},xmm1,xmm2
  5a:	62 e1 75 09 fe e2    	vpaddd xmm20{k1},xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9;
VXORPS XMM10, XMM10, XMM10;
VXORPS XMM11, XMM11, XMM11;
VXORPS XMM12, XMM12, XMM12;
VXORPS XMM16, XMM16, XMM16;
VXORPS XMM17, XMM17, XMM17;
VXORPS XMM18, XMM18, XMM18;
VXORPS XMM19, XMM19, XMM19;
VXORPS XMM20, XMM20, XMM20

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 6.0
- Reference cycles: 5.11
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.25
- UOPS_PORT_1: 5.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.42
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 6.0

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 75 09 fe c2    	vpaddd xmm0{k1},xmm1,xmm2
   6:	62 f1 75 09 fe da    	vpaddd xmm3{k1},xmm1,xmm2
   c:	62 f1 75 09 fe e2    	vpaddd xmm4{k1},xmm1,xmm2
  12:	62 f1 75 09 fe ea    	vpaddd xmm5{k1},xmm1,xmm2
  18:	62 f1 75 09 fe f2    	vpaddd xmm6{k1},xmm1,xmm2
  1e:	62 f1 75 09 fe fa    	vpaddd xmm7{k1},xmm1,xmm2
  24:	62 71 75 09 fe c2    	vpaddd xmm8{k1},xmm1,xmm2
  2a:	62 71 75 09 fe ca    	vpaddd xmm9{k1},xmm1,xmm2
  30:	62 71 75 09 fe d2    	vpaddd xmm10{k1},xmm1,xmm2
  36:	62 71 75 09 fe da    	vpaddd xmm11{k1},xmm1,xmm2
  3c:	62 71 75 09 fe e2    	vpaddd xmm12{k1},xmm1,xmm2
  42:	62 e1 75 09 fe c2    	vpaddd xmm16{k1},xmm1,xmm2
  48:	62 e1 75 09 fe ca    	vpaddd xmm17{k1},xmm1,xmm2
  4e:	62 e1 75 09 fe d2    	vpaddd xmm18{k1},xmm1,xmm2
  54:	62 e1 75 09 fe da    	vpaddd xmm19{k1},xmm1,xmm2
  5a:	62 e1 75 09 fe e2    	vpaddd xmm20{k1},xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9;
VXORPS XMM10, XMM10, XMM10;
VXORPS XMM11, XMM11, XMM11;
VXORPS XMM12, XMM12, XMM12;
VXORPS XMM16, XMM16, XMM16;
VXORPS XMM17, XMM17, XMM17;
VXORPS XMM18, XMM18, XMM18;
VXORPS XMM19, XMM19, XMM19;
VXORPS XMM20, XMM20, XMM20

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 5.35
- Reference cycles: 4.82
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.33
- UOPS_PORT_1: 5.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.33
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 75 09 fe c2    	vpaddd xmm0{k1},xmm1,xmm2
   6:	62 f1 75 09 fe da    	vpaddd xmm3{k1},xmm1,xmm2
   c:	62 f1 75 09 fe e2    	vpaddd xmm4{k1},xmm1,xmm2
  12:	62 f1 75 09 fe ea    	vpaddd xmm5{k1},xmm1,xmm2
  18:	62 f1 75 09 fe f2    	vpaddd xmm6{k1},xmm1,xmm2
  1e:	62 f1 75 09 fe fa    	vpaddd xmm7{k1},xmm1,xmm2
  24:	62 71 75 09 fe c2    	vpaddd xmm8{k1},xmm1,xmm2
  2a:	62 71 75 09 fe ca    	vpaddd xmm9{k1},xmm1,xmm2
  30:	62 71 75 09 fe d2    	vpaddd xmm10{k1},xmm1,xmm2
  36:	62 71 75 09 fe da    	vpaddd xmm11{k1},xmm1,xmm2
  3c:	62 71 75 09 fe e2    	vpaddd xmm12{k1},xmm1,xmm2
  42:	62 e1 75 09 fe c2    	vpaddd xmm16{k1},xmm1,xmm2
  48:	62 e1 75 09 fe ca    	vpaddd xmm17{k1},xmm1,xmm2
  4e:	62 e1 75 09 fe d2    	vpaddd xmm18{k1},xmm1,xmm2
  54:	62 e1 75 09 fe da    	vpaddd xmm19{k1},xmm1,xmm2
  5a:	62 e1 75 09 fe e2    	vpaddd xmm20{k1},xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9;
VXORPS XMM10, XMM10, XMM10;
VXORPS XMM11, XMM11, XMM11;
VXORPS XMM12, XMM12, XMM12;
VXORPS XMM16, XMM16, XMM16;
VXORPS XMM17, XMM17, XMM17;
VXORPS XMM18, XMM18, XMM18;
VXORPS XMM19, XMM19, XMM19;
VXORPS XMM20, XMM20, XMM20

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 5.35
- Reference cycles: 4.82
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.33
- UOPS_PORT_1: 5.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.33
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	62 f1 7d 09 fe c0    	vpaddd xmm0{k1},xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.63
- UOPS_EXECUTED.THREAD: 1.0
- RETIRE_SLOTS: 1.0
- UOPS_MITE: 1.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.34
- UOPS_PORT_1: 0.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.33
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.25

With loop_count=1000 and unroll_count=10

Code:

   0:	62 f1 7d 09 fe c0    	vpaddd xmm0{k1},xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 0.9
- UOPS_EXECUTED.THREAD: 1.1
- RETIRE_SLOTS: 1.1
- UOPS_MITE: 1.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.33
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.3

With loop_count=100 and unroll_count=100

Code:

   0:	62 f1 7d 09 fe c0    	vpaddd xmm0{k1},xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 0.9
- UOPS_EXECUTED.THREAD: 1.01
- RETIRE_SLOTS: 1.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.33
- UOPS_PORT_1: 0.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.34
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	62 f1 7d 09 fe c0    	vpaddd xmm0{k1},xmm0,xmm0
   6:	62 f1 75 09 fe c9    	vpaddd xmm1{k1},xmm1,xmm1
   c:	62 f1 6d 09 fe d2    	vpaddd xmm2{k1},xmm2,xmm2
  12:	62 f1 65 09 fe db    	vpaddd xmm3{k1},xmm3,xmm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 1.91
- Reference cycles: 1.46
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.34
- UOPS_PORT_1: 1.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.33
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.07

With loop_count=1000 and unroll_count=2

Code:

   0:	62 f1 7d 09 fe c0    	vpaddd xmm0{k1},xmm0,xmm0
   6:	62 f1 75 09 fe c9    	vpaddd xmm1{k1},xmm1,xmm1
   c:	62 f1 6d 09 fe d2    	vpaddd xmm2{k1},xmm2,xmm2
  12:	62 f1 65 09 fe db    	vpaddd xmm3{k1},xmm3,xmm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 1.92
- Reference cycles: 1.76
- UOPS_EXECUTED.THREAD: 4.5
- RETIRE_SLOTS: 4.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.31
- UOPS_PORT_1: 1.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.36
- UOPS_PORT_6: 0.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	62 f1 7d 09 fe c0    	vpaddd xmm0{k1},xmm0,xmm0
   6:	62 f1 75 09 fe c9    	vpaddd xmm1{k1},xmm1,xmm1
   c:	62 f1 6d 09 fe d2    	vpaddd xmm2{k1},xmm2,xmm2
  12:	62 f1 65 09 fe db    	vpaddd xmm3{k1},xmm3,xmm3

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 1.91
- Reference cycles: 1.74
- UOPS_EXECUTED.THREAD: 4.05
- RETIRE_SLOTS: 4.05
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.32
- UOPS_PORT_1: 1.34
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.34
- UOPS_PORT_6: 0.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 7d 09 fe c0    	vpaddd xmm0{k1},xmm0,xmm0
   6:	62 f1 75 09 fe c9    	vpaddd xmm1{k1},xmm1,xmm1
   c:	62 f1 6d 09 fe d2    	vpaddd xmm2{k1},xmm2,xmm2
  12:	62 f1 65 09 fe db    	vpaddd xmm3{k1},xmm3,xmm3
  18:	62 f1 5d 09 fe e4    	vpaddd xmm4{k1},xmm4,xmm4
  1e:	62 f1 55 09 fe ed    	vpaddd xmm5{k1},xmm5,xmm5
  24:	62 f1 4d 09 fe f6    	vpaddd xmm6{k1},xmm6,xmm6
  2a:	62 f1 45 09 fe ff    	vpaddd xmm7{k1},xmm7,xmm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 3.75
- Reference cycles: 3.65
- UOPS_EXECUTED.THREAD: 8.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 8.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.66
- UOPS_PORT_1: 2.66
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.67
- UOPS_PORT_6: 0.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.53

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 7d 09 fe c0    	vpaddd xmm0{k1},xmm0,xmm0
   6:	62 f1 75 09 fe c9    	vpaddd xmm1{k1},xmm1,xmm1
   c:	62 f1 6d 09 fe d2    	vpaddd xmm2{k1},xmm2,xmm2
  12:	62 f1 65 09 fe db    	vpaddd xmm3{k1},xmm3,xmm3
  18:	62 f1 5d 09 fe e4    	vpaddd xmm4{k1},xmm4,xmm4
  1e:	62 f1 55 09 fe ed    	vpaddd xmm5{k1},xmm5,xmm5
  24:	62 f1 4d 09 fe f6    	vpaddd xmm6{k1},xmm6,xmm6
  2a:	62 f1 45 09 fe ff    	vpaddd xmm7{k1},xmm7,xmm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 3.82
- Reference cycles: 3.46
- UOPS_EXECUTED.THREAD: 9.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.67
- UOPS_PORT_1: 2.67
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.67
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 7d 09 fe c0    	vpaddd xmm0{k1},xmm0,xmm0
   6:	62 f1 75 09 fe c9    	vpaddd xmm1{k1},xmm1,xmm1
   c:	62 f1 6d 09 fe d2    	vpaddd xmm2{k1},xmm2,xmm2
  12:	62 f1 65 09 fe db    	vpaddd xmm3{k1},xmm3,xmm3
  18:	62 f1 5d 09 fe e4    	vpaddd xmm4{k1},xmm4,xmm4
  1e:	62 f1 55 09 fe ed    	vpaddd xmm5{k1},xmm5,xmm5
  24:	62 f1 4d 09 fe f6    	vpaddd xmm6{k1},xmm6,xmm6
  2a:	62 f1 45 09 fe ff    	vpaddd xmm7{k1},xmm7,xmm7

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 3.82
- Reference cycles: 3.46
- UOPS_EXECUTED.THREAD: 8.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.09
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.67
- UOPS_PORT_1: 2.67
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.67
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	62 f1 7d 09 fe c0    	vpaddd xmm0{k1},xmm0,xmm0
   6:	62 f1 75 09 fe c9    	vpaddd xmm1{k1},xmm1,xmm1
   c:	62 f1 6d 09 fe d2    	vpaddd xmm2{k1},xmm2,xmm2
  12:	62 f1 65 09 fe db    	vpaddd xmm3{k1},xmm3,xmm3
  18:	62 f1 5d 09 fe e4    	vpaddd xmm4{k1},xmm4,xmm4
  1e:	62 f1 55 09 fe ed    	vpaddd xmm5{k1},xmm5,xmm5
  24:	62 f1 4d 09 fe f6    	vpaddd xmm6{k1},xmm6,xmm6
  2a:	62 f1 45 09 fe ff    	vpaddd xmm7{k1},xmm7,xmm7
  30:	62 51 3d 09 fe c0    	vpaddd xmm8{k1},xmm8,xmm8
  36:	62 51 35 09 fe c9    	vpaddd xmm9{k1},xmm9,xmm9
  3c:	62 51 2d 09 fe d2    	vpaddd xmm10{k1},xmm10,xmm10
  42:	62 51 25 09 fe db    	vpaddd xmm11{k1},xmm11,xmm11
  48:	62 51 1d 09 fe e4    	vpaddd xmm12{k1},xmm12,xmm12
  4e:	62 a1 7d 01 fe c0    	vpaddd xmm16{k1},xmm16,xmm16
  54:	62 a1 75 01 fe c9    	vpaddd xmm17{k1},xmm17,xmm17
  5a:	62 a1 6d 01 fe d2    	vpaddd xmm18{k1},xmm18,xmm18

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9;
VXORPS XMM10, XMM10, XMM10;
VXORPS XMM11, XMM11, XMM11;
VXORPS XMM12, XMM12, XMM12;
VXORPS XMM16, XMM16, XMM16;
VXORPS XMM17, XMM17, XMM17;
VXORPS XMM18, XMM18, XMM18

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 7.65
- Reference cycles: 6.57
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.34
- UOPS_PORT_1: 5.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.01
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.34
- UOPS_PORT_6: 0.0
- UOPS_PORT_7: 0.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.15

With loop_count=1000 and unroll_count=1

Code:

   0:	62 f1 7d 09 fe c0    	vpaddd xmm0{k1},xmm0,xmm0
   6:	62 f1 75 09 fe c9    	vpaddd xmm1{k1},xmm1,xmm1
   c:	62 f1 6d 09 fe d2    	vpaddd xmm2{k1},xmm2,xmm2
  12:	62 f1 65 09 fe db    	vpaddd xmm3{k1},xmm3,xmm3
  18:	62 f1 5d 09 fe e4    	vpaddd xmm4{k1},xmm4,xmm4
  1e:	62 f1 55 09 fe ed    	vpaddd xmm5{k1},xmm5,xmm5
  24:	62 f1 4d 09 fe f6    	vpaddd xmm6{k1},xmm6,xmm6
  2a:	62 f1 45 09 fe ff    	vpaddd xmm7{k1},xmm7,xmm7
  30:	62 51 3d 09 fe c0    	vpaddd xmm8{k1},xmm8,xmm8
  36:	62 51 35 09 fe c9    	vpaddd xmm9{k1},xmm9,xmm9
  3c:	62 51 2d 09 fe d2    	vpaddd xmm10{k1},xmm10,xmm10
  42:	62 51 25 09 fe db    	vpaddd xmm11{k1},xmm11,xmm11
  48:	62 51 1d 09 fe e4    	vpaddd xmm12{k1},xmm12,xmm12
  4e:	62 a1 7d 01 fe c0    	vpaddd xmm16{k1},xmm16,xmm16
  54:	62 a1 75 01 fe c9    	vpaddd xmm17{k1},xmm17,xmm17
  5a:	62 a1 6d 01 fe d2    	vpaddd xmm18{k1},xmm18,xmm18

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9;
VXORPS XMM10, XMM10, XMM10;
VXORPS XMM11, XMM11, XMM11;
VXORPS XMM12, XMM12, XMM12;
VXORPS XMM16, XMM16, XMM16;
VXORPS XMM17, XMM17, XMM17;
VXORPS XMM18, XMM18, XMM18

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 7.66
- Reference cycles: 7.08
- UOPS_EXECUTED.THREAD: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.33
- UOPS_PORT_1: 5.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.33
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	62 f1 7d 09 fe c0    	vpaddd xmm0{k1},xmm0,xmm0
   6:	62 f1 75 09 fe c9    	vpaddd xmm1{k1},xmm1,xmm1
   c:	62 f1 6d 09 fe d2    	vpaddd xmm2{k1},xmm2,xmm2
  12:	62 f1 65 09 fe db    	vpaddd xmm3{k1},xmm3,xmm3
  18:	62 f1 5d 09 fe e4    	vpaddd xmm4{k1},xmm4,xmm4
  1e:	62 f1 55 09 fe ed    	vpaddd xmm5{k1},xmm5,xmm5
  24:	62 f1 4d 09 fe f6    	vpaddd xmm6{k1},xmm6,xmm6
  2a:	62 f1 45 09 fe ff    	vpaddd xmm7{k1},xmm7,xmm7
  30:	62 51 3d 09 fe c0    	vpaddd xmm8{k1},xmm8,xmm8
  36:	62 51 35 09 fe c9    	vpaddd xmm9{k1},xmm9,xmm9
  3c:	62 51 2d 09 fe d2    	vpaddd xmm10{k1},xmm10,xmm10
  42:	62 51 25 09 fe db    	vpaddd xmm11{k1},xmm11,xmm11
  48:	62 51 1d 09 fe e4    	vpaddd xmm12{k1},xmm12,xmm12
  4e:	62 a1 7d 01 fe c0    	vpaddd xmm16{k1},xmm16,xmm16
  54:	62 a1 75 01 fe c9    	vpaddd xmm17{k1},xmm17,xmm17
  5a:	62 a1 6d 01 fe d2    	vpaddd xmm18{k1},xmm18,xmm18

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM3, XMM3, XMM3;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
VXORPS XMM6, XMM6, XMM6;
VXORPS XMM7, XMM7, XMM7;
VXORPS XMM8, XMM8, XMM8;
VXORPS XMM9, XMM9, XMM9;
VXORPS XMM10, XMM10, XMM10;
VXORPS XMM11, XMM11, XMM11;
VXORPS XMM12, XMM12, XMM12;
VXORPS XMM16, XMM16, XMM16;
VXORPS XMM17, XMM17, XMM17;
VXORPS XMM18, XMM18, XMM18

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 7.66
- Reference cycles: 7.03
- UOPS_EXECUTED.THREAD: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MITE: 0.16
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.33
- UOPS_PORT_1: 5.33
- UOPS_PORT_2: 0.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.33
- UOPS_PORT_6: 0.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

VPADDD (XMM, K, XMM, XMM) - Throughput and Uops

With different registers for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With the same register for for different operands

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10