VPERMT2W (YMM, K, YMM, YMM) - Throughput and Uops (IACA 3.0)


With different registers for different operands

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 6.80 Cycles       Throughput Bottleneck: Backend
Loop Count:  38
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.5     0.0  |  0.5  |  0.0     0.0  |  0.0     0.0  |  0.0  |  2.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   3      | 0.5         | 0.5  |             |             |      | 2.0  |      |      | vpermt2w ymm0{k1}, ymm1, ymm2
Total Num Of Uops: 3

With 16 independent instructions


Throughput Analysis Report
--------------------------
Block Throughput: 31.89 Cycles       Throughput Bottleneck: Backend
Loop Count:  22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  8.0     0.0  |  8.0  |  0.0     0.0  |  0.0     0.0  |  0.0  | 32.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   3      | 1.0         |      |             |             |      | 2.0  |      |      | vpermt2w ymm0{k1}, ymm1, ymm2
|   3      |             | 1.0  |             |             |      | 2.0  |      |      | vpermt2w ymm3{k1}, ymm1, ymm2
|   3      | 1.0         |      |             |             |      | 2.0  |      |      | vpermt2w ymm4{k1}, ymm1, ymm2
|   3      |             | 1.0  |             |             |      | 2.0  |      |      | vpermt2w ymm5{k1}, ymm1, ymm2
|   3      | 1.0         |      |             |             |      | 2.0  |      |      | vpermt2w ymm6{k1}, ymm1, ymm2
|   3      |             | 1.0  |             |             |      | 2.0  |      |      | vpermt2w ymm7{k1}, ymm1, ymm2
|   3      | 1.0         |      |             |             |      | 2.0  |      |      | vpermt2w ymm8{k1}, ymm1, ymm2
|   3      |             | 1.0  |             |             |      | 2.0  |      |      | vpermt2w ymm9{k1}, ymm1, ymm2
|   3      | 1.0         |      |             |             |      | 2.0  |      |      | vpermt2w ymm10{k1}, ymm1, ymm2
|   3      |             | 1.0  |             |             |      | 2.0  |      |      | vpermt2w ymm11{k1}, ymm1, ymm2
|   3      | 1.0         |      |             |             |      | 2.0  |      |      | vpermt2w ymm12{k1}, ymm1, ymm2
|   3      |             | 1.0  |             |             |      | 2.0  |      |      | vpermt2w ymm16{k1}, ymm1, ymm2
|   3      | 1.0         |      |             |             |      | 2.0  |      |      | vpermt2w ymm17{k1}, ymm1, ymm2
|   3      |             | 1.0  |             |             |      | 2.0  |      |      | vpermt2w ymm18{k1}, ymm1, ymm2
|   3      | 1.0         |      |             |             |      | 2.0  |      |      | vpermt2w ymm19{k1}, ymm1, ymm2
|   3      |             | 1.0  |             |             |      | 2.0  |      |      | vpermt2w ymm20{k1}, ymm1, ymm2
Total Num Of Uops: 48

With the same register for for different operands

Throughput Analysis Report
--------------------------
Block Throughput: 6.80 Cycles       Throughput Bottleneck: Backend
Loop Count:  38
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.5     0.0  |  0.5  |  0.0     0.0  |  0.0     0.0  |  0.0  |  2.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   3      | 0.5         | 0.5  |             |             |      | 2.0  |      |      | vpermt2w ymm0{k1}, ymm0, ymm0
Total Num Of Uops: 3