CMPXCHG_LOCK (M16, R16) - Throughput and Uops (IACA 2.1)
With a non-indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 3.00 Cycles Throughput Bottleneck: InterIteration
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 1.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4^ | 1.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | | 1.0 | CP | lock cmpxchg word ptr [r14], r8w
Total Num Of Uops: 4
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles Throughput Bottleneck: FrontEnd, Port0, Port1, Port5
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 1.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4^ | 1.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | | 1.0 | CP | lock cmpxchg word ptr [r14], r8w
| 0* | | | | | | | | xor rax, rax
Total Num Of Uops: 4
With 16 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 48.00 Cycles Throughput Bottleneck: InterIteration
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 16.0 0.0 | 16.0 | 8.0 8.0 | 8.0 8.0 | 0.0 | 16.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14], r8w
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0x2], r8w
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+0x4], r8w
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0x6], r8w
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+0x8], r8w
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0xa], r8w
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+0xc], r8w
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0xe], r8w
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+0x10], r8w
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0x12], r8w
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+0x14], r8w
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0x16], r8w
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+0x18], r8w
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0x1a], r8w
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+0x1c], r8w
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0x1e], r8w
Total Num Of Uops: 64
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 16.00 Cycles Throughput Bottleneck: FrontEnd, Port0, Port1, Port5
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 16.0 0.0 | 16.0 | 8.0 8.0 | 8.0 8.0 | 0.0 | 16.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14], r8w
| 0* | | | | | | | | xor rax, rax
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0x2], r8w
| 0* | | | | | | | | xor rax, rax
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+0x4], r8w
| 0* | | | | | | | | xor rax, rax
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0x6], r8w
| 0* | | | | | | | | xor rax, rax
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+0x8], r8w
| 0* | | | | | | | | xor rax, rax
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0xa], r8w
| 0* | | | | | | | | xor rax, rax
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+0xc], r8w
| 0* | | | | | | | | xor rax, rax
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0xe], r8w
| 0* | | | | | | | | xor rax, rax
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+0x10], r8w
| 0* | | | | | | | | xor rax, rax
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0x12], r8w
| 0* | | | | | | | | xor rax, rax
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+0x14], r8w
| 0* | | | | | | | | xor rax, rax
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0x16], r8w
| 0* | | | | | | | | xor rax, rax
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+0x18], r8w
| 0* | | | | | | | | xor rax, rax
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0x1a], r8w
| 0* | | | | | | | | xor rax, rax
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+0x1c], r8w
| 0* | | | | | | | | xor rax, rax
| 4^ | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+0x1e], r8w
| 0* | | | | | | | | xor rax, rax
Total Num Of Uops: 64
With an indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 3.00 Cycles Throughput Bottleneck: InterIteration
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 1.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4 | 1.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1], r8w
Total Num Of Uops: 4
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 1.25 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 1.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4 | 1.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | | 1.0 | | lock cmpxchg word ptr [r14+r13*1], r8w
| 0* | | | | | | | | xor rax, rax
Total Num Of Uops: 4
With 16 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 48.00 Cycles Throughput Bottleneck: InterIteration
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 16.0 0.0 | 16.0 | 8.0 8.0 | 8.0 8.0 | 0.0 | 16.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1], r8w
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1+0x2], r8w
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1+0x4], r8w
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1+0x6], r8w
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1+0x8], r8w
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1+0xa], r8w
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1+0xc], r8w
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1+0xe], r8w
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1+0x10], r8w
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1+0x12], r8w
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1+0x14], r8w
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1+0x16], r8w
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1+0x18], r8w
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1+0x1a], r8w
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1+0x1c], r8w
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | CP | lock cmpxchg word ptr [r14+r13*1+0x1e], r8w
Total Num Of Uops: 64
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 20.00 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 16.0 0.0 | 16.0 | 8.0 8.0 | 8.0 8.0 | 0.0 | 16.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | | lock cmpxchg word ptr [r14+r13*1], r8w
| 0* | | | | | | | | xor rax, rax
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | | lock cmpxchg word ptr [r14+r13*1+0x2], r8w
| 0* | | | | | | | | xor rax, rax
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | | lock cmpxchg word ptr [r14+r13*1+0x4], r8w
| 0* | | | | | | | | xor rax, rax
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | | lock cmpxchg word ptr [r14+r13*1+0x6], r8w
| 0* | | | | | | | | xor rax, rax
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | | lock cmpxchg word ptr [r14+r13*1+0x8], r8w
| 0* | | | | | | | | xor rax, rax
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | | lock cmpxchg word ptr [r14+r13*1+0xa], r8w
| 0* | | | | | | | | xor rax, rax
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | | lock cmpxchg word ptr [r14+r13*1+0xc], r8w
| 0* | | | | | | | | xor rax, rax
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | | lock cmpxchg word ptr [r14+r13*1+0xe], r8w
| 0* | | | | | | | | xor rax, rax
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | | lock cmpxchg word ptr [r14+r13*1+0x10], r8w
| 0* | | | | | | | | xor rax, rax
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | | lock cmpxchg word ptr [r14+r13*1+0x12], r8w
| 0* | | | | | | | | xor rax, rax
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | | lock cmpxchg word ptr [r14+r13*1+0x14], r8w
| 0* | | | | | | | | xor rax, rax
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | | lock cmpxchg word ptr [r14+r13*1+0x16], r8w
| 0* | | | | | | | | xor rax, rax
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | | lock cmpxchg word ptr [r14+r13*1+0x18], r8w
| 0* | | | | | | | | xor rax, rax
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | | lock cmpxchg word ptr [r14+r13*1+0x1a], r8w
| 0* | | | | | | | | xor rax, rax
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | | lock cmpxchg word ptr [r14+r13*1+0x1c], r8w
| 0* | | | | | | | | xor rax, rax
| 4 | 1.0 | 1.0 | | 1.0 1.0 | | 1.0 | | lock cmpxchg word ptr [r14+r13*1+0x1e], r8w
| 0* | | | | | | | | xor rax, rax
Total Num Of Uops: 64
With the -no_interiteration flag
Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles Throughput Bottleneck: Port0, Port1, Port5
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 1.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4^ | 1.0 | 1.0 | 0.5 0.5 | 0.5 0.5 | | 1.0 | CP | lock cmpxchg word ptr [r14], r8w
Total Num Of Uops: 4