IDIV (R8l)

With unroll_count=500 and no inner loop

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
   e:	f6 fb                	idiv   bl

Init:
```
MOV BL, 1;
MOV RAX, 0;
MOV RDX, 0
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.0
- Reference cycles: 3.58
- UOPS_EXECUTED.THREAD: 6.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.31
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.35
- UOPS_PORT_6: 1.34
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With unroll_count=500 and no inner loop

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
   e:	f6 fb                	idiv   bl
  10:	0f ae e8             	lfence

Init:
```
MOV BL, 1;
MOV RAX, 0;
MOV RDX, 0
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 27.2
- Reference cycles: 16.3
- UOPS_EXECUTED.THREAD: 6.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 6.0
- UOPS_MS: 2.0
- UOPS_PORT_0: 0.6
- UOPS_PORT_1: 2.6
- UOPS_PORT_5: 1.4
- UOPS_PORT_6: 1.4
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
   e:	f6 fb                	idiv   bl

Init:
```
MOV BL, 1;
MOV RAX, 0;
MOV RDX, 0
```
Show nanoBench command
Results:
- Instructions retired: 3.2
- Core cycles: 6.0
- Reference cycles: 3.59
- UOPS_EXECUTED.THREAD: 6.1
- RETIRE_SLOTS: 6.1
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.3
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.32
- UOPS_PORT_6: 1.49
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
   e:	40                   	rex
   f:	40                   	rex
  10:	40                   	rex
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40 f6 fb             	rex idiv bl

Init:
```
MOV BL, 1;
MOV RAX, 0;
MOV RDX, 0
```
Show nanoBench command
Results:
- Instructions retired: 3.2
- Core cycles: 6.0
- Reference cycles: 3.59
- UOPS_EXECUTED.THREAD: 6.1
- RETIRE_SLOTS: 6.1
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.3
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.32
- UOPS_PORT_6: 1.48
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
   e:	f6 fb                	idiv   bl

Init:
```
MOV BL, 1;
MOV RAX, 0;
MOV RDX, 0
```
Show nanoBench command
Results:
- Instructions retired: 3.02
- Core cycles: 6.0
- Reference cycles: 3.59
- UOPS_EXECUTED.THREAD: 6.01
- RETIRE_SLOTS: 6.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.31
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.34
- UOPS_PORT_6: 1.36
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
   e:	40                   	rex
   f:	40                   	rex
  10:	40                   	rex
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40 f6 fb             	rex idiv bl

Init:
```
MOV BL, 1;
MOV RAX, 0;
MOV RDX, 0
```
Show nanoBench command
Results:
- Instructions retired: 3.02
- Core cycles: 6.0
- Reference cycles: 3.59
- UOPS_EXECUTED.THREAD: 6.01
- RETIRE_SLOTS: 6.01
- UOPS_MITE: 0.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.32
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.33
- UOPS_PORT_6: 1.36
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With unroll_count=500 and no inner loop

Code:

   0:	66 b8 01 33          	mov    ax,0x3301
   4:	f6 fb                	idiv   bl

Init:
```
MOV BL, 123
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 16.0
- Reference cycles: 9.54
- UOPS_EXECUTED.THREAD: 5.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 3.0
- UOPS_MITE>=1: 1.0

With unroll_count=500 and no inner loop

Code:

   0:	66 b8 01 33          	mov    ax,0x3301
   4:	f6 fb                	idiv   bl
   6:	0f ae e8             	lfence

Init:
```
MOV BL, 123
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 27.6
- Reference cycles: 16.47
- UOPS_EXECUTED.THREAD: 5.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 5.0
- UOPS_MS: 2.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 3.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	66 b8 01 33          	mov    ax,0x3301
   4:	f6 fb                	idiv   bl

Init:
```
MOV BL, 123
```
Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 16.0
- Reference cycles: 9.56
- UOPS_EXECUTED.THREAD: 5.1
- RETIRE_SLOTS: 5.1
- UOPS_MITE: 5.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.01
- UOPS_PORT_6: 1.11
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 3.01
- UOPS_MITE>=1: 1.1

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	66 b8 01 33          	mov    ax,0x3301
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	40                   	rex
   e:	40                   	rex
   f:	40 f6 fb             	rex idiv bl

Init:
```
MOV BL, 123
```
Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 16.0
- Reference cycles: 9.56
- UOPS_EXECUTED.THREAD: 5.1
- RETIRE_SLOTS: 5.1
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.99
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 1.11
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	66 b8 01 33          	mov    ax,0x3301
   4:	f6 fb                	idiv   bl

Init:
```
MOV BL, 123
```
Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 16.0
- Reference cycles: 9.56
- UOPS_EXECUTED.THREAD: 5.01
- RETIRE_SLOTS: 5.01
- UOPS_MITE: 5.02
- UOPS_MS: 0.01
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 3.01
- UOPS_MITE>=1: 1.01

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	66 b8 01 33          	mov    ax,0x3301
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	40                   	rex
   e:	40                   	rex
   f:	40 f6 fb             	rex idiv bl

Init:
```
MOV BL, 123
```
Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 16.0
- Reference cycles: 9.56
- UOPS_EXECUTED.THREAD: 5.01
- RETIRE_SLOTS: 5.01
- UOPS_MITE: 0.05
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 2.0
- UOPS_PORT_5: 1.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_23: 0.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- DIV_CYCLES: 6.0
- ILD_STALL.LCP: 0.03
- UOPS_MITE>=1: 0.01

IDIV (R8l) - Throughput and Uops

Fast division

With unroll_count=500 and no inner loop

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Slow division

With unroll_count=500 and no inner loop

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)