VPERMILPS_EVEX (XMM, M32_1to4, I8)

Operands

• Operand 1 (w): Register (XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, XMM16, XMM17, XMM18, XMM19, XMM20, XMM21, XMM22, XMM23, XMM24, XMM25, XMM26, XMM27, XMM28, XMM29, XMM30, XMM31)
• Operand 2 (r): Memory
• Operand 3 (r): 8-bit immediate

Available performance data

• Alder Lake-P
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• AMD Zen 4

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤8
  • Latency operand 2 → 1 (address, index register): ≤8
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 1.00 (if an indexed addressing mode is used: 0.33)
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (4 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23A+1*p5 (if an indexed addressing mode is used: 1*p23A)

Rocket Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤8
  • Latency operand 2 → 1 (address, index register): ≤8
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5

Tiger Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤8
  • Latency operand 2 → 1 (address, index register): ≤8
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5

Ice Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤8
  • Latency operand 2 → 1 (address, index register): ≤8
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5

Cascade Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤8
  • Latency operand 2 → 1 (address, index register): ≤8
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5

Cannon Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤8
  • Latency operand 2 → 1 (address, index register): ≤8
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5

Skylake-X

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤8
  • Latency operand 2 → 1 (address, index register): ≤8
  • Latency operand 2 → 1 (memory): ≤5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p23+1*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p23+1*p5

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤9
  • Latency operand 2 → 1 (address, index register): ≤9
  • Latency operand 2 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.33
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
• Port usage: 1*FP123