VPERMT2W (YMM, K, YMM, YMM)

Operands

• Operand 1 (r/w): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15, YMM16, YMM17, YMM18, YMM19, YMM20, YMM21, YMM22, YMM23, YMM24, YMM25, YMM26, YMM27, YMM28, YMM29, YMM30, YMM31)
• Operand 2 (r): Register (K1, K2, K3, K4, K5, K6, K7)
• Operand 3 (r): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15, YMM16, YMM17, YMM18, YMM19, YMM20, YMM21, YMM22, YMM23, YMM24, YMM25, YMM26, YMM27, YMM28, YMM29, YMM30, YMM31)
• Operand 4 (r): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15, YMM16, YMM17, YMM18, YMM19, YMM20, YMM21, YMM22, YMM23, YMM24, YMM25, YMM26, YMM27, YMM28, YMM29, YMM30, YMM31)

Available performance data

• Emerald Rapids
• Alder Lake-P
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• AMD Zen 5
• AMD Zen 4

Emerald Rapids

• Measurements
• Latencies
  • Latency operand 1 → 1: 9
  • Latency operand 2 → 1: 5
  • Latency operand 3 → 1: 8
  • Latency operand 4 → 1: 8
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+2*p5

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1: 9
  • Latency operand 2 → 1: 5
  • Latency operand 3 → 1: 8
  • Latency operand 4 → 1: 8
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+2*p5

Rocket Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 9
  • Latency operand 2 → 1: 5
  • Latency operand 3 → 1: 8
  • Latency operand 4 → 1: 8
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+2*p5

Tiger Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 9
  • Latency operand 2 → 1: 5
  • Latency operand 3 → 1: 8
  • Latency operand 4 → 1: 8
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+2*p5

Ice Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 9
  • Latency operand 2 → 1: 5
  • Latency operand 3 → 1: 8
  • Latency operand 4 → 1: 8
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+2*p5
• Documentation
• Throughput: 2.0

Cascade Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 9
  • Latency operand 2 → 1: 5
  • Latency operand 3 → 1: 8
  • Latency operand 4 → 1: 8
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+2*p5

Cannon Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 9
  • Latency operand 2 → 1: 5
  • Latency operand 3 → 1: 8
  • Latency operand 4 → 1: 8
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+2*p5

Skylake-X

• Measurements
• Latencies
  • Latency operand 1 → 1: 9
  • Latency operand 2 → 1: 5
  • Latency operand 3 → 1: 8
  • Latency operand 4 → 1: 8
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 3
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+2*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00
• Number of μops: 3
• Port usage: 1*p015+2*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 1.99
• Number of μops: 3
• Port usage: 1*p015+2*p5

AMD Zen 5

• Measurements
• Latencies
  • Latency operand 1 → 1: 4
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1: 4
  • Latency operand 4 → 1: 4
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.46
• Number of μops
  • Executed: 1
• Port usage: 1*FP12
• Documentation
• Latency: 4
• Throughput: 0.50
• Number of μops: 1
• Port usage: FP1/2

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 1 → 1: 4
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1: 4
  • Latency operand 4 → 1: 4
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
• Port usage: 1*FP12
• Documentation
• Latency: 4
• Throughput: 0.50
• Number of μops: 1
• Port usage: FP1/2